The symbol/BiTrit "S" (0,0) during a data word means "repeat the precedent biTrit". I have limited the number of repetitions of this meta-sequence to allow clock recovery and reduce droop, but I have found that limiting to 1 S is too hard on the circuit if it is parallelized. This is important because we want to be able to evaluate the "droop" of a whole world in parallel and this info is important.

So we get 20 bits, extended to 21 with the LSB cleared for now, and compare pairs of tribits. The first tribit is not subject to substitution, so there are 6 such comparisons, each with 3×XOR2 and 1×NOR3. Here is the circuit:

So far, nothing weird.

The trick is to "length limit" the sequences of Tx=1. Of the 64 possible cases, 20 have a "suppressed" bit:

000111 00011x
001110 0011x0
001111 0011x1
010111 01011x
011100 011x00
011101 011x01
011110 011x10
011111 011x11
100111 10011x
101110 1011x0
101111 1011x1
110111 11011x
111000 11x000
111001 11x001
111010 11x010
111011 11x011
111100 11x100
111101 11x101
111110 11x110
111111 11x11x

There is only one case where the suppression occurs twice, but this would be more complex with only 1 Same only.

With 2 consecutive "Same" bitrits, the circuit is somewhat shorter:

Total depth: 7 gates.

See you in the next log.