Jerry Hubbell12:29 PM
Just signed up for the pilot.

Hemal Chevli12:31 PM
if you just reading the gerbers, how are the net names known, or this only available if a kicad/eagle board uploaded?

Mark J Hughes12:32 PM
@Hemal -- the gerbers do not have the information you need -- you need extended gerber v2 or IPC2581 or KiCad files.

Ragabash12:32 PM
Signed up

Mihir Shah12:33 PM
what other info/data would you want to see overlaid? dmm readings? scope waveforms? EDA simulations?

Jerry Hubbell12:33 PM
A thermal image overlay would be nice

Ragabash12:34 PM
Sometimes net length can be really useful for finding where highspeed nets go wrong. Reflections happen at discontinuities in impedance so being able to pinpoint those would be great

Mark J Hughes12:34 PM
@Jerry Hubbell We've begun to experiment with the FlirOne.

amigabill12:34 PM
Pdn voltage region, current

Alistair Cheeseman12:34 PM
can you overlay altium's PDN analyzer graphics?

amigabill12:35 PM
net names

Ragabash12:35 PM
Would be nice to be able to turn on .steo/3d models so it's easy to compare against the real thing - easy to improve CAD quality

Ragabash12:35 PM
*.stpe

Ragabash12:35 PM
.step

Jerry Hubbell12:36 PM
What kind of automation or scripting might be good to add?

Mark J Hughes12:37 PM
@Ragabash inspectAR2.0 will be ready for that. We are integrating 3D board tracking. Turning on the step file layer shouldn't be a problem from a technical standpoint. The detail of the step models could overwhelm a phone's processor in a complicated design. It's something we can implement and if there is interest, we can add it to our roadmap.

Ragabash12:38 PM
pick and place data, incase rotations of placements are wrong

Mark J Hughes12:39 PM
@Ragabash I'm curious -- has that ever happened to you? I've not run into that problem yet.

We usually go an hour, but that's up to you

Jerry Hubbell12:40 PM
Thank you

amigabill12:40 PM
Bare board connections for probing opens/shorts before assembly

Ragabash12:41 PM
Yeah, one GPS module recently was 180 degrees out. Was an error in part library creation as a non-standard part

Hemal Chevli12:41 PM
sorry if I missed it, are through-hole, blind and buried vias visualized differently?

Mihir Shah12:43 PM
mihir@inspectar.com

Mihir Shah12:43 PM
for any additional questions!

Sounds good.

Hemal Chevli12:44 PM
Thanks its was a great demo!

Jerry Hubbell12:44 PM
Thanks for a great look at InspectAR I appreciate it.

It's really come a long way since the Supercon talk. Very impressive!

Ragabash12:44 PM
Thanks for the demo, I look forward to trying it out

Just curious, Mihir, and somewhat tangential, but how is Royal doing with the shutdown. Are you essential enough to keep things running?

OK, looks like we lost everyone. I'll just wrap it up with a big thanks to Mihir and Liam for their time and the great demo. I'll post the transcript soon, and the video as soon as I get it. Everything will be at https://hackaday.io/event/169986-pcb-bring-up-hack-chat

Mihir Shah12:54 PM
Royal is doing really well! fully up and running, building a lot of boards for Medtronic and the ventilators

And don't forget next week we have the Apollo Guidance Computer team:

https://hackaday.io/event/170569-hacking-apollo-hack-chat

HACKADAY

Hacking Apollo Hack Chat

The Apollo Guidance Computer team will host the Hack Chat on Wednesday, April 22, 2020 at noon Pacific Time. Time zones got you down? Here's a handy time converter! When President Kennedy laid down the gauntlet to a generation of scientists and engineers to land a man on the Moon before the close of the 1960s, he likely had little idea what he was putting in motion.

Read this on Hackaday

Mihir Shah12:55 PM
arguably busier than ever since most other shops are closed down, and china is slow