Dan Maloney
OK, folks, good afternoon/evening/morning to you all. We're ready to kick off the Hack Chat! I'm Dan, I'll be moderating today along with Dusan for Hackaday's own Al Williams!
Hi everyone!
Hi Al!
Hello
Good to see everyone virutally
I just saw Al over on the event page chat, asked him to pop over here.
There we go -- hi Al!
Hey Al, Dan
I'm in multiple places at once....
That sounds like something from the DSM-V...
Ah but the more we know about where you are the less we know about your energy state
How's your cat Bil?
Lol... good. Lost the turkey in the cold snap tho...
Ready to go Dan?
Good to see everyone here...
Ok well let me say a few things about simulation and then we can just kind of freewheel with wherever we want to go with the topic.
Oh yes, by all means -- how about a little about yourself for those who don't know you?
Well, most of you know me from Hackaday and the old among us will remember I was with Dr. Dobb’s Journal and some other magazines back when magazines were made from forest products. Let’s see… I seem to bounce around between things… my undergraduate degree is about 80% EE but I finished with a CS degree (long story). Then I have a Master’s in EE from Columbia (the University, not the country which is spelled different).
So I’ve done software ranging from low-level assembly to BIOS code. Hardware design from the die level to vacuum tubes to FPGAs. I have designs that have been at the bottom of the ocean and in orbit. I’ve been a ham radio operator for about 45 years or so. I’ve written a bunch of books and a while back I wrote the FPGA bootcamp series that is on hackaday.io.
We actually started out with Bootcamp #1 which uses Verilog, but after talking to some people, I found out that many people really needed to learn just the fundamentals of digital logic. So we did bootcamp #0 which uses online tools to do simulations in your browser. Of course, the Verilog is also a simulation (until it is compiled) and that can be in your browser, too.
It reminds me of when I was in school a very long time ago. We learned drafting with T-squares and pencils. But we had two weeks of “computer aided drafting” where we punched cards like: rectangle(20,20,100,195) and circle(15,30,44). At the time, I thought that was stupid because the future was drawing stuff on the computer.
But if you look at modern CAD tools, they do let you “code” things so you can have parametric CAD. Some tools like OpenSCAD that’s all you do. If you are making a donut shape, drawing is OK. But if you are making something complex, modeling the relationships is more efficient in the long run. So this also happens with simulations. A lot of people – me included – start learning about Verilog and think that it is stupid because you can just draw schematics. But when you have a CPU with tens of thousands of gates, the schematic entry gets clunky fast. Verilog or VHDL or something like that is the way to go. Consider this 7 segment decoder: http://tinyurl.com/ybqfbk6m
Vs this one:
always @(*)
case (number)
4'h0: dispoutput <= 7'b1111110; // all segments but center
4'h1: dispoutput <= 7'b0110000; // two segments to form "1"
4'h2: dispoutput <= 7'b1101101; // five segments to form "2"
. . .
Amazing, a Hack Chat with someone that types faster than 1 sentence per 3 minutes!
So a few random topics we could chat about...
Schematic entry vs HDL.
What doesn’t simulate well?
What does simulate well
Mixed mode simulation
What’s your favorite simulator?
Simulation with a CPU model included (Did you know Falstad can do that? https://hackaday.com/2021/06/11/circuit-vr-arduino-virtually-meets-analog/ – several others, too)
Hardware in the loop simulation
Quantum simulators
Optimization - gates vs speed vs packages vs ???
You tell me…. What do you want to talk about?
You've heard of hunt and peck? Maybe cut and paste lol
I "cheat" and use the vendor specific tools such as Altera and Xylinx, what are the open source alteratives?
You compiled your notes, professor!
How about a "Best choice for beginners" in logic simulators?
oh good evening!
I submit that Al is really a simulation (ssshhh... don't tell him)
Al or AI?
So...
Didn't know Falstad had CPU models, sweet!
I guess the first thing to think about is what you want to accomplish
I saw recently some apps to pull circuit diagrams from images. Then lots of groups doing SPICE circuit simulations. And lots of videos of beginners (hackers) drawing circuits by hand, and then mumbling half remembered rules for how to calculate basic voltages, currents, couplings and frequencies.
Falstad has the advantage of being no setup. You can even do sort of mixed modes. So for play it isn't bad at all. But serious stuff... maybe not so much.
I use H. Neemann's "Digital" simulator - It's takes over from where LogiSim went down.
https://github.com/hneemann/Digital
I am like Bill. If I'm using a device I will use the vendor tools because they have really good models for it.
Falstad could probably get more serious if it were converted to web assembly
Yes I like Digital as well
Digital (outputs HDL): https://github.com/hneemann/Digital (has java components, serial port, CPU, etc.)
Falstad probably is fine like it is for what it is
Great visualization
But if you do anything serious schematic entry is ponderous
When I worked for Motorola we used to literally crawl over the schematics for the 68000 on a giant table in our lab
Honestly would get up on the table and crawl on our hands and knees to read them.
So for anything serious you really want the HDL type simulations
At least you didn't have to draft the transistors by hand....
You had 1s? lol
I will say though Bil
Yes - I heard about the table-crawling when they laid out the 6502 at MOS. Clean socks, with no holes essential....
For quick HDL I really love EDAPlayground and we use it in the bootcamps
EDAPlayground: http://edaplayground.com/
Lol... yes
In browser and access to a lot of commerical-quality and FOSS tools with no setup or install
Again, probably not what you want to base the rest of your career on but very cool
One thing I like about Digital by the way
looks like a good way to develope or test snippets
is you can draw schematics and get a truth table or start with a truth table and it will do a schematic. Plus you can export VHDL or Verilog
So that's nice because you can start with a simple schematic / logic diagram and then move to verilog
The other nice thing about the vendor tools is they will optimize for the architecture when you build anyway so getting optimal is less important than it used to be... especially since optimal changes depending on what you want
Is the exported VHDL any good or do you find you have to re-work it?
Al - any thoughts about hosting a Digital bootcamp, to bring schematics and HDL into a common learning resource?
For example, when I was in school we were taught to get down to all one kind of gate because in those days you probably had one kind of gate you used for everything (discrete transistors). But with SSI like 7400 chips, it was better to use fewer packages
I don't do much with VHDL these days but the Verilog is good enough. I have not tried anything huge with it though
any opinion on cypress' PSoC Creator?
I did notice the last release notes from a few weeks ago said that it had some Verilog fixes in it
I haven't gone all the way thru the boot camps yet, looking to buy some ice40 hw too. At what complexity do the open source tools start to break down?
Bootcamp for Digital... maybe. I wanted to do some more FPGA bootcamps with development of a UART etc but we were getting increasingly small numbers as the bootcamps wet up in number lol
i really like psoc creator, its one of the rare tools where a primarily hardware company makes decent software
Is there any sort of mental break you need to make when using logic simulators to design for FPGA versus when you want to build something from, say, a bunch of 74xx chips?
PSoC... what a great idea. I love the concept but honestly I haven't used the latest gen of the tool suite. For those of you who don't know
PSoC has a CPU (or several) and some uncommitted logic and analog blocks you can configure ... sort of like an FPGA but at a higher level
I think there are a few answers to Dan's question
Verilog is like a knife... it can chop, carve, or stab
So depending on what you want out of it, it can be very little different or very different
As a simulation language you can actually model down to the gate level in Verilog
I found PSOC usable at least for small stuff.
And you can naively transcribe gates.... and(q,a1,a2,a3);
But the smart money is on telling Verilog what you want and letting the FPGA synthesis figure that out.
So it is like my 7 segment example that I used at the top
Logic simulation should be independent of whether it's in an FPGA or a pile of TTL. Timing simulation depends on modeling gate delays and interconnect. This is automatically extracted for FPGAs, but not for board of TTL.
its good for stuff like ws style programmable led /capacitive touch projects since you can implement the WS driver on the block side and not have to struggle with the tight timing and theyre cheap
You could write all the AND OR gates etc. but why? Just describe it. Phillip makes a good point, although I will disagree slightly. In FPGA design there are really two levels of sim
Functional is where you make sure you figured out what you want it to do
But you also do post synthesis simulation to make sure you get timing right and miss race condiditions/metastability and so on
s/condiditions/conditions
lol
So then it does matter and the gate-level sim makes sense there along with vendor models for temperature and clocking
Have you tried moving any of your FPGA designs in to an ASIC ecosystem like Skywater PDK? If so, what were your biggest challenges?
Speaking of metastability that is one place where many of the tools you commonly use don't work well is at the rough edges. ... so if you have a 2ps glitch or a time of metastabiity
I have not done FPGA to ASIC. I've done ASIC professionally where we go straight from sim to ASIC. You really want your simulations correct then because being wrong can cost you your job or your company lol
Of course, digital is really analog at the bottom and you can simulate with something like LTSpice and it isn't even that hard
I am reading these, thinking that you are only describing tools for individuals. Tools that require lots of memorization and practice. Tools that do not scale, and tools that are NOT good at collaboration. When you were crawling the 68000, there was a group. Each person did what they were best at, and not all of them were soldering, or editing circuits on the computer, or ordering parts, or trying to raise funds. You really have not said what you want to make. I know of thousands of global scale problems. You are just talking about tools for part of a problem for one person. What about things that matter? Or problems that cut across many people on Hackaday.io?
That lets you set up horrible simulations with analog issues. And do mixed signal.
Altera supposedly had an FPGA to ASIC program but whenever I asked for details no-one from Altera could speak to it.
For example: LTSpice can simulate digital:
Functional sim works best in a single clock environment, and static timing analysis is sufficient for verification of meeting timing. Things get way more messy with two or more independent clock domains. FPGA vendor timing models tend to only do worst case timing, ignoring some of the hazards of a best case situation, (for CMOS: high VDD and low temp)
The timing between FPGA and ASIC can be a lot different but you'd think it could work pretty well
there are some of those neat looking asic/fpga combo chips never used one but from what i understand they have the programmable and dedicated layers going on
We also did a nice set of YouTube videos on LTSpice in general awhile back along with the Circuit VR series
A serious challenge of migrating from FPGA to ASIC is the constraints system and test vectors (or equiv) may not be compatible.
Yeah well a lot of ASIC is cell based. So instead of a programmable interconnect you basically just do a single layer of metal on top
Yah the contraints in particular. That's one area where it would be nice to have a single ecosystem for both
I just asked a chip guy using 7nm ASIC and he said they had 22 layers of metal and 76 masks total, way more than the old days
It is not hard to model digital devices, or systems of any sort - including all the analog elements. And, nowadays, they all depend on software, algorithms, setting goals, and collaboration between people working globally.
Yeah or however many metalization layers you have. All the chips are flipped upside down now too
also FPGA is constrained by input terms of the LUTs that doesn't necessarily carry over to ASIC.
or so my memory goes
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