Chat Transcript, Page 2

benbojangles 3:48 PM

vr/mixed reality sbc?

benbojangles 3:49 PM

allow users to work on an android/linux vr port

eben.upton 3:49 PM

benbojangles - historically would have been a bit "picking winners" (our word for doing engineering with is very focused on a specific vertical market)

eben.upton 3:50 PM

but we do do things now (Pi 500, monitor) which are both more "complete" as products, and more focused on a specific use case or user story than we did in the past

eben.upton 3:50 PM

so never say never

benbojangles 3:51 PM

any word on pi sbc that will incorporate nvivdia cuda gpu?

eben.upton 3:51 PM

I hear Jeff may have made some progress with non-AMD GPUs recently

Evan 3:52 PM

More like a GPU that incorporates a Pi, lol

eben.upton 3:52 PM

benbojangles 3:52 PM

i agree it would be better to have a more open gpu provider than nvidia

benbojangles 3:52 PM

especially for linux

eben.upton 3:53 PM

just amazing what they've accomplished with the CUDA ecosystem though

Jan Hamal Dvořák 3:53 PM

@eben.upton: And (probably) last question from me. Any chance of expanding DSP functionality on RP2s? I am thinking of e.g. couple FIFOs for DMA to sync on, possibly usable as Ts and Wyes to (de)interleave streams, at least two adders that can be fed and sampled by DMA, maybe full-blown CIC if you can fit the adders.

eben.upton 3:53 PM

how we used to laugh at the NVIDIA guys at Khronos when they said in the future most compute would happen on GPUs

Fred 3:53 PM

nvidia ai hat for RPI....

benbojangles 3:53 PM

haha

Fred 3:54 PM

do some coda rpi style

Fred 3:54 PM

*cuda

eben.upton 3:54 PM

Jan - if there's a sketch of something (with some use cases) we could think about it. We've sort of shied away from adding compute to the PIO/DMAverse, but it's not impossible.

dratini0 3:55 PM

There are also ways to run/port/etc CUDA code to non-Nvidia GPUs, but I have forgotten all the details.

eben.upton 3:56 PM

The challenge is that a lot of the AI models are somewhat co-evolved with the NVIDIA microarchitecture. That's a very deep moat.

benbojangles 3:56 PM

wifi 7 coming to pi? It would make excellent bandwidth streaming

eben.upton 3:57 PM

WiFi 5 has been good to us across Pi 3+, 4, and 5, but I suspect we've probably shipped out last flagship product with that tech.

Fred 3:58 PM

any hints on "most requested RPI features" Eben?

benbojangles 3:58 PM

yes, there are big changes happening in wifi tech now

eben.upton 3:58 PM

Well, a power button and an RTC :)

Fred 3:59 PM

PI5 power - check

Evan 3:59 PM

I'm still voting for the ability to sleep

keithpenney 3:59 PM

Yes, with wake-on-LAN

eben.upton 3:59 PM

I'm not sure there's much else. Suspend/resume, which is getting some attention (but is incredibly hard to make robust to our standards, as other people have found).

benbojangles 4:00 PM

it's less than 1w power, why need to sleep so much?

dratini0 4:00 PM

IIRC the wifi chip is attached via SDIO. What are the limitations of that, and would you need to upgrade that if you went for wifi 6 or newer?

eben.upton 4:00 PM

Ah, our posts crossed.

Fred 4:00 PM

really cool with the extra risc core Pico 2

eben.upton 4:00 PM

Actually SDIO is very bandwidthful in its highest speed incarnations.

dratini0 4:00 PM

Neat

eben.upton 4:01 PM

But I suspect (and this is a long way away) you'd want to provision the Pi 6 SoC with a PCIe lane for WiFi. Actually the most attractive aspect is finally getting rid of the damn UART for BT.

eben.upton 4:02 PM

Well, thank you everyone. I have to go read LOTR to my daughter in a minute, but time for one last question if there is one.

Richard Unger 4:02 PM

Hi! I have one burning question: can you share any news on when the RP2350 will be available to purchase for use in our own designs, via digikey, or similar? Having played with the Pico2, I'm looking forward to using it :-)

Fred 4:02 PM

many thanks Eben!!! Take care!

Dan Maloney 4:02 PM

Bringing the next generation up right -- nice

eben.upton 4:02 PM

thanks Fred

eben.upton 4:02 PM

100%

Steve Markgraf 4:02 PM

@Richard Unger I just wanted to ask the same ;)

eben.upton 4:02 PM

Richard - they've been on JLC for roughly a month.

Electronic Eel 4:03 PM

Could you explain in more detail why you decided not to give the user full access to the ARM cores of the RP1 that is on the Pi5? That would allow to make fast use of the PIO units there and so on. It would probably allow to circumvent the security of the OS, but I guess this could be protected by requiring a special kernel module and giving only root access to it.

eben.upton 4:03 PM

But now we've done the results of the Hacking Challenge we'll be pushing A and B variants out on Raspberry Pi Direct, and the usual distie channels ASAP.

eben.upton 4:03 PM

This month, hopefully.

Dan Maloney 4:03 PM

Thanks so much for stopping by today, this was a great way to kick off the year! Thanks Eben, and thanks to everyone for tagging along with such great questions

dratini0 4:03 PM

Thank you for answering all these questions, and I'm very glad the "RP1 on a PCIe card" idea isn't categorically impossible!

Richard Unger 4:03 PM

Thank you!

Szaja 4:04 PM

Thanks!

Steve Markgraf 4:04 PM

Thanks as well!

eben.upton 4:05 PM

Mr Eel - answer is upthread. Lack of desire to get people hooked on the rather "special" RP1 processor subsystem, in the belief that, in the ten-year timeframe, it's likely to get replaced with something more "standard" (i.e. RP2-like).

eben.upton 4:05 PM

G'night all.

Dan Maloney 4:05 PM

The transcript will be a little delayed, but we should have it up this afternoon. Thanks everyone!

Electronic Eel 4:05 PM

@eben.upton thanks

Boian Mitov 4:06 PM

Thank you @eben.upton and @Dan Maloney :-)

Jan Hamal Dvořák 4:06 PM

Thanks!

mwsecdev 4:08 PM

Thanks. Very interesting....

Chat Transcript, Page 1

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