ASIC Design Hack Chat

Let's talk mixed signal ASIC design for Oscilloscopes!

Hack Chat

Event Details

Join the ASIC Design chat by clicking on the JOIN HACK CHAT button. Then, request to join #Hack Chat. Don't request to join from this page, click the JOIN HACK CHAT button.

Come and talk with @matthew_martin, ASIC designer at Keysight.

Matt graduated from CU Boulder in 2006, with a M.S. in Electrical Engineering, B.S. in Electrical and Computer Engineering, and a B.S. in Applied Math.

He started working at Agilent (now Keysight) in 2007 as a physical designer for digital ASICs. Physical design is sometimes referred to as backend work; Matt starts after the code that describes the functionality of the chip has been synthesized into logic gates, and takes it all the way to a design that can be fabricated in silicon. He has designed ASICs in process nodes from 0.13um to 28nm, with a variety of applications from control blocks for primarily analog signal conditioning chips to large digital data processors.

In his spare time, he enjoys working on scales visible to the naked eye, like home renovation and board games.

We're meeting over at the #Hack Chat on March 17th, noon PDT.

The list for discussion and questions is here.

Event Logs

Collapse

ASIC #HackChat Transcript
Shulie Tornel • 03/17/2017 at 19:51 • 0 comments

Matt Martin Shall we get started? Does anyone currently here have any questions?
kevin.harrelson Did you shave this year for St. Baldrick's?
Shulie Tornel Questions for Matt can go here: https://docs.google.com/spreadsheets/d/13FvkrHwB7J1SAaQ_DPHPR4GszRTAtCUoA-5rf4jZPmw/edit#gid=0
Shulie Tornel If chat is laggy, please just click refresh!
Matt Martin I'll start by introducing myself. My name is Matt Martin, and I work in Keysight's ASIC design group. I do physical design for digital and mixed ASICs.
Matt Martin am also joined by Daneil Bogdanoff, who works in the oscilloscope division, and can help answer some of the more oscilloscope specific questions, as opposed to ASIC questions
Shulie Tornel Welcome @Matt Martin Thanks for participating!
Paul Stoffregen any chance for hints about future keysight products?
Daniel Bogdanoff Haha, paul, not the place for that :)
Matt Martin And to answer Kevin's question about St. Baldricks, my profile picture is only a few days old. But, I will be making a donation in the future when my hair is long enough.
pop13 Did keysight made the 1000x series intentionally hackable?
Matt Martin OK, so starting from the spreadsheet, I think Dave's question "How much is the cost of one ASIC in quantity one?" is a good place to start
Matt Martin And the answer is... A LOT
pop13 :D
Daniel Bogdanoff It's easily millions of dollars
Daniel Bogdanoff but older processes can be cheaper
pop13 Ia m not thinking when it was still in dev state but like RIGHT NOW
Matt Martin So, the way ASICs are manufactured involves a large up front cost in engineering design. Once that design is complete, the foundry takes it and makes a mask set for photolithography. These masks are used to process wafers of silicon, yeilding tens to hundreds of die per wafer
Matt Martin So, it's hard to get just a single die
Matt Martin The actual cost per die depends on the process node the design is done in and the size and yield of the die
Matt Martin Some smaller signal conditioning ASICs are <$10 for a packaged and tested part
Matt Martin Big DSP chips can run into the hundreds of dollars
pop13 I ment the megazoom ASICs (if you can talk about it)
Paul Stoffregen Is all the scope's buffer memory actually on the asic die? I have a 4000x scope and I've used others from time to time and it's just amazing how much more responsive yours is.
kevin.harrelson Matt: I can field the MegaZoom question if you want... If I am allowed.
Matt Martin This is also a good lead in to 6th question "Any reasons to have separate linked dies, or is it more common to be etched onto the same silicon?"
Daniel BogdanoffThe cost of the specific ASICs is proprietary, but's it's definiltey more than a few bucks
Matt Martin Different process nodes have different performance characteristics
Daniel BogdanoffAnd the memory is built into the ASIC itself, which is why the scopes are so response
Daniel Bogdanoff responsive
Matt Martin Which also leads explains question 7 "Where are ASICS primarily used in scopes today? Is it mostly for high speed sampling, logic analyzer portions that are increasingly being incorporated? Mixed signal or mostly digital?"
pop13 So for the PCB guys its easy, just whack the ASIC down on the board, no external RAM etc.
Daniel Bogdanoff That's a big reason we use asics in our scopes because we can tune the hardware to be efficient for the specific processing tasksi
Daniel Bogdanoff instead of using an off-the-shelf processor
Matt Martin The basic block diagram for a scope has a signal conditioning front end, sending an analog signal into an ADC, which then ships digital data to a DSP/memory chip
Daniel Bogdanoff It's also not a freebie for the PCB team, though, ASICs are sensitive
Daniel Bogdanoff Can you briefly discuss the advantages of using a ASIC rather than an off the shelf ADC+FPGA, as are commonly used in low end scopes?
Matt Martin For the big digital chips, more advanced process nodes (meaning smaller transistor geometries) allow us to incorporate more logic and therefore...
Read more »

View event log

Discussions

keith77777 wrote 03/14/2017 at 23:18

Yes you can apply windowing to enable full scale resolution by altering DC shift and gain, as can done on analogue scopes. Also if there is a lot of noise then its pointless having more resolution. But when you compare digital with analogue scopes the only parameter is one shot bandwidth and averaging in digital scopes is OK for repeditive waveforms. I would think the ccd memory and slow speed A to D would be a good way of obtaining increased resolution. I believe RIGOL use interleaved A to D in one of their scopes. I will stick to my TEK7904.

Are you sure? yes | no

keith77777 wrote 03/14/2017 at 18:52

Looked at digital scopes and thought of buying one but they are all 8 bit unless u pay a fortune. Philips had ccd analogue memory in some of their scopes. If I was a programmer I would think of hacking a PC tv card should be ok to 20 MHz. The chipsets in these are A to D with memory closely linked.

Are you sure? yes | no

K.C. Lee wrote 03/14/2017 at 19:07

A scope is more than just A/D converters. There are signal conditioning, attenuation selection for the ranges, bandwidth limit switch, triggering hardware and a lot of signal processing firmware for the under sampling to work. :P

Are you sure? yes | no

K.C. Lee wrote 03/14/2017 at 19:21

http://www.tek.com/blog/not-so-high-high-resolution

https://www.ecnmag.com/article/2013/01/how-get-more-8-bits-your-8-bit-scope
In real life "8-bit" doesn't means Effective number of bits (ENOB) once you figure in the noise floor, nonlinearity of the analog stages.

Are you sure? yes | no

Frederik Dubois wrote 03/14/2017 at 20:35

You can achieve a really good voltage resolution on your oscilloscope with only a 8 bit a/d front end. The hardware offset and gain adjustment are applied before going to the ADC. The full range of the 8 bit ADC is always displayed on the screen (correct me if i'm wrong), so if you change the vertical scale on your scope, an hardware gain is applied before the ADC so the bottom of your osc's screen is the adc value 0 and the top of the screen is always 255. If you want better vertical resolution, crank up the scale dial! But then you'll need to consider the noise of the front end chain.
I think that the key is not an ADC with more bits, but a front end with lower noise so you can apply more input gain thus better voltage resolution with only 8 bit.

Are you sure? yes | no

ASIC Design Hack Chat

Become a Hackaday.io member

Just one more thing

Event Details

Event Logs Collapse

ASIC #HackChat Transcript

Enjoy this event?

Discussions

Become a Hackaday.io Member

Interested in attending?

Report project as inappropriate

Send message

Remove Member

Event Logs

Collapse