I've decided to switch to a hardware sequenced microarchitecture for the Kestrel-3 CPU. It will be built just like the 6502 was: it will have a two-stage pipeline (fetch and execute), both operated under a single micro-sequencer, and the microarchitecture will be very tightly coupled to the bus interface.

The CPU's clock will be 25MHz. The bus clock will be 12.5MHz. Since each instruction is 32-bits wide, and the bus is only 16-bits wide, it takes two bus cycles (at a minimum) to execute an instruction (thus, 4 clocks). These four 25MHz cycles conveniently maps to two register-fetch cycles (allowing me a single-ported register file), an execute cycle, and a write-back cycle. Thus, most (if not all) OP-IMM or OP-REG instructions ought to run in two bus cycles (four 25MHz cycles). 25MHz / 4 = 6.25 MIPS, so best-case, we're preserving my intended level of performance.

Loads and stores will necessarily incur a performance hit, though, since they must compete for access to the bus. Bytes and half-words incur an additional 2 cycles, words an additional 4 cycles, and double-words an additional 8 cycles.

Performance of other CPU features is up in the air, but I think this covers 99% of what anyone would run on the CPU anyway.

ALSO, the new supervisor specification is out, so I think now would be a good time to update the emulator to match the new RISC-V supervisor requirements. I'll resume work on the CPU once that's done.