I've been so busy and distracted of late, I rather forgot I had this project website!

Recently, I've been working on building the Kestrel-3 Verilog sources.  I'm starting out with a very simple DMA Controller (DMAC) core, whose responsibility it is to just sequentially scan through memory, and read the results back through a series of attached LEDs.  If done slowly enough, this will permit me to read out the contents of flash ROM and confirm that I am programming it and the FPGA bitstream correctly at a human scale.  BUT, to interface to the flash ROM, I must further build another core, called ROMA, for ROM Adapter.  This will couple the 64-bit TileLink TL-UL interface to the bit-serial, SPI-based interface that the flash ROM resides on.

I've been recording my progress via a video blog, which is named Over the Shoulder II (a long awaited sequel to my original Over the Shoulder video on using Forth in development).  I've recorded four episodes so far:

https://peertube.mastodon.host/videos/watch/b3a870d6-a2f9-4560-8837-1a0200352c93

https://peertube.mastodon.host/videos/watch/8ce25ead-b643-48e3-a633-1ab5e73b019f

https://peertube.mastodon.host/videos/watch/4d393226-a70f-4f7c-bea1-1973fd9f7c8b

https://peertube.mastodon.host/videos/watch/dd97c19d-4cdc-4d95-9a36-e07f6a60d78c

Over time, I'll be adding more videos, as I find the time to work further on the project.

What's in store for episode 5?  Well, hopefully, a change in format that won't be quite as boring to the viewer.  The Bob Ross-like approach to watching me work seems to work great as long as you can contain everything in a single video.  Beyond that, viewership drops off asymptotically.  More poignantly, though, hopefully a simulated-working ROMA core.  :)