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CGIA Dot Shifter Verilog Almost Done.

A project log for Kestrel Computer Project

The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.

samuel-a-falvo-iiSamuel A. Falvo II 06/15/2016 at 15:110 Comments

Since I'm still operating in a different timezone from everyone else around me, I decided to use the three hour sleep schedule difference to work some more on the CGIA.

First, I decided to split the CGIA into its own repository. When it comes time to integrate it into an actual chip, I'll just refer to it by git submodule. I know that it's a bit of a burden to do so, but this buys me two benefits: first, it makes it more reusable to people in general, and second, it lets me package the core up into something that the FuseSoC package manager can use. Note: as I write this article, I'm doing all my work in my personal fork, so don't expect to find much in the official repo yet. I'll land my WIP as soon as I'm done with the dot shifter implementation.

Which brings me to the second point, where I'm happy to say that I've implemented a video shift register capable of shifting by 1, 2, 4, or 8 bits at a time. This register is a hard requirement to support 2, 4, 16, or 256 color depths. Note that these are "chunky" video modes, not planar.

Using the shift register is a module called the "shifter" (named after the Atari ST's video chip), which is responsible for taking the output of the shift register above and putting the appropriate color palette index out onto a "color bus." Though, I'm probably going to rename "color bus" to "index bus" to avoid confusion after inserting the palette registers.

Things that remain to be supported include an index XOR mask, which would let lower color depths make use of all 256 palette registers; also, I need to add logic to the shifter to actually read the contents of the line buffer. I think I'll call the shifter done-for-now after I finish these two things.

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