Update on FPGATED drop in IC replacement.

The drop-in TED replacement's biggest challenges are

- the analogous part of the IC (Luma and Chroma generator)

- component sizes on the PCB to fit the small space in the Plus4's metal cage (C16 is not an issue)

Over the last months I have been investigating these and created some proof of concepts. Unfortunately I had to rule out the using of an external video signal generator like the AD724/AD725 IC because the RF modulator of Plus4 and C16 delays the chroma signal too much (about 100ns) which requires a luma delay circuit to get them in phase. Delaying an analogous signal is much more difficult than delaying digital one thus I have turned to a different approach.

The luma signal can be created relatively easily in the FPGA using LUT for the luma values and requires just a few external components (resistors) before connecting to the RF modulator. Here the only challenge is the external voltage levels which should be between 0 - 4.8v. This part has been solved.

The chroma signal requires DDS to create the sine wave and modulate its phase. This is not too difficult either, however it requires some careful planning in order to have an optimal design and not to over complicate things. Some of the questions are, how large should be the phase accumulator and the DAC resolution? Do we need a high precision DAC? What should be the internal clock frequency for the DDS keeping in mind that we need to implement PAL and NTSC both? I have done simulations in Matlab which shows some good results using 12bits phase accumulator (no truncation) and 6 bits DAC.

 Again the biggest challenge is how can I fit all these components to the small PCB? I need to find an optimal FPGA in physical size, most probably with BGA package. 

TED module needed some modification too because I have not yet implemented the burst signal which is also handled by the horizontal events decoder. In addition an output buffer enable signal is needed from TED to signal when it puts data to the databus (e.g. when we read one of its registers). This signal controls the FPGA's bidirectional data bus IO pins and not available on the final IC legs.

The result will be shared when it is the right time.