Manufacturing required to fill all empty spaces by some filling cells that have metal layers and poly to meet density rule - this should support all neighboring designs. I created this cell 10x10um with 3 metal layers and poly layer connected to each other:

This is how CIF-viewer showed this (and how it looks on actual silicon - with "fingers"):

Problem is (and I think it's main reason of chips slowness) there is no connection to the ground (P-substrate here)! So chip is having a lot of floating capacitors between signals and ground that eat all dynamic - it has to be fixed before 2nd tapeout...