I have studied the data RAM ( Read/Write circuit) but the instruction memory is not designed yet.

Actually I have not designed an instruction set or format so the following discussion will remain very prospective.

Magnetic memory wouldn't work with relay logic levels. The RAM needs to be refreshed too often. So far the only method that makes sense is an array of switches and diodes.

Ted inspired me to design a modular system with boards that can be swapped in/out for convenient programming and reuse of common code routines, so at least 4 boards are required in a bus. I suppose each board could contain about 32 instructions...

With this modular approach I can implement the program memory boards with various methods :

• DIP switches for easy development (but they are not cheap)
• 0.1" male headers with jumpers for more stable code (a bit cheaper but don't lose the jumpers)
• soldered diodes on a higher density matrix for stable libraries (math routines ?)

To ease development, a companion board should be created to provide a visual aid for assembly and disassembly. This is the same idea as the #Discrete YASEP's "hardware assembler" but with relays ;-) Now, maybe the "hardware assembler" should be simply integrated in the actual instruction decoder, to save on hardware and keep up with any ISA changes. A switch will simply determine if the current instruction comes from a front panel (easy for single stepping) or one of the boards... The front panel will provide a first practical interface to develop and debug the execution unit while the actual program counter and instruction memory are being developed.

So basicly, we have an electrical interface : X instruction bits and a strobe...

20161117

TODO : when a code routine is done, hardwire it with RED LED. More voltage drop but OMG it will look so amazing !

20161121

The LED will not sustain enough current to switch the coils (60mA)

Since there will be several program boards of different types, let's ponder what the first ROM will do : initialise all the CCPBRL states to a known value and contain the routine that refreshes the DRAM.

The refresh routine might work as an interrupt and needs to save a few registers before doing its job so a few (2? 4?) scratch registers are needed. How to implement them is a new question to answer...