The design has had from the start the ability to have the host PC access the external static RAM of the FPGA board. This has been super handy for loading test firmware and TI-99/4A ROMS and other programs.

However, the design goal from the beginning was that the PC could read and write the external SRAM concurrently to the TMS99105 CPU. While that has been possible, there was no provision to manage bus contention properly, so that the TMS99105 would not notice the accesses. I did not want to use traditional DMA access using the HOLD input of the CPU, nor did I want to use wait states, as the external SRAM on the Pepino board is very fast.

Now I did a very minor change, which seems to work well and allows the host PC to access the memory, both reading and writing, without any impact to the CPU. I simply now use the time that the CPU is outputting memory addresses over its multiplexed address/data bus to provide a nice access window for the PC. The ALATCH signal is active roughly a quarter of the 200ns machine (and memory access) cycles, yielding something like 50ns for the FPGA to provide an access window for the PC communication state machine to access the memory.

This same repeatedly occurring access window could also be used for other purposes than the PC memory access state window. Since the ALATCH cycles occur repeatedly every 200ns, the access windows are there all the time. The PC accesses originate from a relatively low speed serial port (230kbps over USB), so they occur very seldom. Since the memory bus on this board is 32-bits wide, just simply using the access windows would give 1/200ns*4 bytes = 20Mbytes of memory bandwidth outside of the CPU use. This is fast enough to feed the video circuit. Also I'm pretty sure that by organising the CPU memory access windows better, the hardware could do multiple accesses during the time the CPU does not need the bus.

The updated VHDL code is at GitHub.