The computer being designed here is centered around the epRISC ISA, a custom 32-bit RISC instruction set architecture that's been in constant development for a little over a year. Version one of the computer implemented v4 of this ISA - the first to be functional enough for its intended use. Version two of the computer was also slated to use the v4 ISA, with a few minor tweaks to boost performance and fix outstanding bugs. With the boards still on their way from the manufacturer, I've been spending my time editing the ISA.

At first, it was fine. A few more arithmetic instructions here, a clarification to interrupt behavior there, and so on. But I soon realized that there were a few things that couldn't really be fixed without ripping up something bigger above it, and when I went to rework those objects they revealed even bigger architectural problems. Slowly, the changes added up, until I realized that I was essentially starting over. So I did.

The current version of the ISA is now v5. It's primary goal is to correct the problems that made v4 hard to implement or use, such as:

• Condition codes - although they made programming easier, they stood in the way of pipelined implementations of the ISA and were thus replaced with conditional branches.
• Vague interrupt behavior - the interrupt system was poorly designed and poorly documented, so everything is being retooled.
• Slow byte access - arithmetic operations have been added that dramatically decrease the number of instructions required to access an arbitrary byte within a 32-bit word, in some places by a full 50%.
• Terrible documentation - the original datasheet for the ISA was poorly written and didn't match the reference implementation at all in some areas; the new datasheet will hopefully be much clearer and much more descriptive.

The changes aren't final yet, but if you'd like to see where things are headed, everything's available in the GitHub repository.