The ALU section of the design contains a 4-bit register A (74HC173D), and a 4-bit register B(74HC173D). These are individually addressable but the main 4-bit data bus, and provide output only to the "ALU". The ALU section consists of a 4-bit full adder 74HC283D, and is supplemented with a quad XOR from register B, which enables 4-bit subtraction. The ALU output is latched into a separate 4-bit register labeled as the Accumulator, which has an selectable output to the main 4-bit databus. This design was directly inspired by the SAP-1 (Simple as Possible) attributed to Paul Malvino (not Ben Eater as some would believe). As a debug item, I've added LEDs on the main data bus to indicate what is being presented on the bus at any given cycle...