In this log I will take a deeper dive into the operation of the circuit. 

The circuit is designed to be stable starting with the buffer capacitor empty. As we attach the power source to the input of the voltage on the buffer capacitor slowly rises on the buffer capacitor. The FlipFlop selected is 74AUP series of digital circuits that have minimal operating voltage of 0.7V but it output starts changing at voltages as low as 0.2V.

As soon as the voltage on the capacitor rises to approximately 0.2V the output Q of the FF matches the supply voltage and starts powering the voltage detector. The circuit continues operation until the activation voltage threshold is reached.

Once the threshold has been reached the output of the voltage detector changes from 0V to VDD. The output of the voltage detector is tied to the CLK input of the FF. The voltage change is interpreted as a rising edge by the FF and the output is changed. As the D output of the FF is tied to ground the Q output goes low thus disabling the Voltage Detector while opening the PMOS that is controlling the power to the load. 

Once the load is done performing work it would place a pulse on the reset line of the power management that resets the FF disabling the power to the load and re-enabling the voltage detector. The process repeats itself when the voltage on the capacitor reaches the threshold voltage