I started with a few template classes:

Wire<N> - generic wires (base class for everything else)

Uint<N> - unsigned N-bit integer 

Sint<N> - signed N-bit integer

Tint<N> - balanced ternary N-trit integer

Also there is class Signal that is the same thing as Wire<1> (a single wire)

Every wire may be in one of the states listed below:

NC - not connected (internally represented by character 'Z')

TRUE - connected to positive power line (internally represented by character 'P')

FALSE - connected to negative power line (internally represented by character 'N')

MAYBE - intermediate state to simulate ternary logic (internally represented by character 'O')

PULLUP - weak pull-up to positive (character '1')

PULLDOWN - weak pull-down to negative (character '0')

INVALID - invalid state that prevents simulated circuit to work properly (character '?')

In future I want to support fixed point and floating point numbers (but not right now).

Sample code to test basic types:

#include "TRCMath.hpp"

using namespace std;

using namespace TRC;

int main()
{
  Wire<5> a;
  Wire<32> b; 
  Wire<1> signal,out;
  Signal signal2;
  Uint<32> u;
  Sint<32> s;
  s[0] = TRUE;
  b[31] = FALSE;
  s = b&&u;
  signal = MAYBE;
  signal2 = TRUE;
  out = signal & signal2;
  cout << "signal=" << signal << endl;
  cout << "signal2=" << signal2 << endl;
  cout << "out=" << out << endl;
  cout << "a=" << a << endl;
  cout << "b=" << b << endl;
  cout << "u=" << u << endl;
  cout << "s=" << s << endl;
}

Objects Wire<N> will support only logical operations and all integer simulated types will support also arithmetic.  Above you can see how operator && (bitwise AND) was applied to two Wire<32> objects and operator & (logical AND) was applied to two Signal objects.

Source code is available under GPLv3 on GitLab (it is still work in progress):

https://gitlab.com/ternary/trcm/blob/master/TRCMath.hpp

Now I'm thinking about the way to support reliable multiple state machine simulation (with ability to run simulation concurrently to occupy all available cores of host PC).