Of course two ALU 's can be cascaded to get a byte-wide ALU.

But you can get a small gain for the adding speed, when the second nibble is slightly changed.

The following diagram shows the path that the carry signal takes through the adder. The numbers indicate the number of parts that the carry-in signals have to pass in worst case. It can be used to optimize the carry speed.

151 --> 8-input multiplexer for fast carry

153 --> 4-input multiplexer for "normal" carry calculation

86  --> XOR port that produces the final output.

As you see, when both nibbles are equal (left diagram), the output of bit 7 will be the slowest, even slower than the byte-carry output.

The diagram at the right shows that bit7 is now faster. Now bit 6 is the slowest output bit, with 4 delays at the input of its XOR gate.