There are several groups of latches scattered around the CPU, which can be collectively named as "Flags register". 

The Status Register - 4 flags to store some properties of ALU operation result. These flags are updated only at ALU operation, or by special MOV, otherwise they stay intact during execution of other operations. Their contents influence results of conditional jumps.

Prefixes - 4 flags for multi-word operations and 1 flag for byte transfer. These are located in Multi-word Transfer Enabler circuit that is integrated with the sequencer. The multi-word transfers are applicable to regular MOVs and memory accesses via memory pointer. The byte transfer flag is only affecting memory access operations. These 5 flags can only be explicitly set by "prefix" instructions - they are cleared automatically after transferring a number of words/bytes according to particular flag. The "byte" flag is working in parallel to the "multi-word operation" flags, so one can set the byte flag together with multi-word transfer flag, and then execute load instruction, thus loading several bytes in consecutive registers. All these flags are cleared at the end of this Load operation execution.

The Multi-word Transfer Enabler makes some states to repeat several times in row (the looping arrows from the state into the same state on the State Machine diagram).

The operations for setting "Prefixes" flags are in "Miscellaneous" group.

Interrupt Masks - several flags (for now I think that 7 or 8 may be needed), that can be set or cleared using operations from "miscellaneous" group. These flags are meant to differentiate interrupts by priority, so that while serving high-priority interrupt, the low-priority ones are ignored or put on queue. This part for now is least defined. 

The Interrupt Masks group of latches/flags are to be placed in Interrupt Controller circuit that is yet to be developed. The sequencer itself only sees if there is interrupt request pending or not.