The CPU has a simple 8-bit microcode:

MICROCODE INSTRUCTIONS
 bytecode
 0x00         LD B,(HL+nn)   ; nn = 0-7 or 0x8000 - 0x8007
 0x10         LD B,(nn)

 0x20         LD L,(HL+nn)
 0x30         LD L,(nn)

 0x80         ST (HL+nn),B
 0x90         ST (nn),B

 0xa0         LD UPC,BL   ; UPC[0-7] <- B[0-7], UPC[8-11] <- L[0-3] 
 0xb0         LD UPC,B    ; UPC[0-7] <- B[0-7], UPC[8-11] <- 0 

 0xc8         LD H,L+nn ; nn = 0-7  IR3 must be set to 'write' to ROM
 0xd8        LD H,nn   ; nn = 0-7  IR3 must be set to 'write' to ROM

 0x00 - 0x07   add this to bytecode for nn = 0-7
 0x08          add this to bytecode for nn = 0x8000 - 0x8007

 Microcode instructions can have an additional M or P, to 
 make them conditional:

  M (minus) -> execute when H[7] = 1
  P (plus)  -> execute when H[7] = 0  

Note that the micro-instruction that writes to H will also write to the external bus, due to the simplicity of the decoder. To prevent writing rubbish to RAM, this micro-instruction has IR3=1 to generate an address in the 0x8000-0xFFFF range. The external address decoding should be such that RAM and I/O is in the 0x000-0x7FFF range, in order not to be corrupted by this decoder effect.

Also note that the "+" in (HL+nn ) is actually a bitwise-OR and not an addition.