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Passing dhrystone in custom simulator

A project log for RISCV SoftCPU for 2018 Contest

RISC-V SoftCPU for the offical contest 2018

antti-lukatsAntti Lukats 10/19/2018 at 08:500 Comments

The trick to compile the dhrystone properly without chaning the dhrystone code was to append LL to HZ definiation in utils.c

This is correct output to be expected from the dhrystone test, please note that the "mcycle=.." should also come unless you have changed the syscalls.c from riscv benchmark github too much!

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