Yann Guidon / YGDESUpdated 20190328
Updated 20190411 : 50 more gates !
For those who are not familiar with the Actel nomenclature, I have included below the definition of the gates that are implemented so far. This is not exhaustive and I might have omitted many gates because I don't need them (but Christos added more).
Of course, some definitions are redundant (by swapping pins or inverting functions and levels: for example NAND2 = OR2C) but they are practical and it is optimised later (with aliases ?).
gate_AND2.vhdl: Y <= A and B after gate_delay;
gate_AND2A.vhdl: Y <= (not A) and B after gate_delay;
gate_AND3.vhdl: Y <= (A and B) and C after gate_delay;
gate_AND3A.vhdl: Y <= ((not A) and B) and C after gate_delay;
gate_AND3B.vhdl: Y <= ((not A) and (not B)) and C after gate_delay;
gate_AND3C.vhdl: Y <= ((not A) and (not B)) and (not C) after gate_delay;
gate_AO1.vhdl: Y <= (A and B) or C after gate_delay;
gate_AO12.vhdl: Y <= ((not A) and B) or ((not A) and (not C)) or (B and (not C)) or (A and (not B) and C) after gate_delay;
gate_AO13.vhdl: Y <= (A and B) or (A and (not C)) or (B and (not C)) after gate_delay;
gate_AO14.vhdl: Y <= (A and B) or (A and (not C)) or (B and (not C)) or ((not A) and (not B) and C) after gate_delay;
gate_AO15.vhdl: Y <= (A and (not B) and C) or ((not A) and B and C) or ((not A) and (not B) and (not C)) after gate_delay;
gate_AO16.vhdl: Y <= (A and B and (not C)) or ((not A) and (not B) and C) after gate_delay;
gate_AO17.vhdl: Y <= (A and B and C) or ((not A) and B and (not C)) or ((not A) and (not B) and C) after gate_delay;
gate_AO18.vhdl: Y <= ((not A) and B) or ((not A) and (not C)) or (B and (not C)) after gate_delay;
gate_AO1A.vhdl: Y <= ((not A) and B) or C after gate_delay;
gate_AO1B.vhdl: Y <= (A and B) or (not C) after gate_delay;
gate_AO1C.vhdl: Y <= ((not A) and B) or (not C) after gate_delay;
gate_AO1D.vhdl: Y <= ((not A) and (not B)) or C after gate_delay;
gate_AO1E.vhdl: Y <= ((not A) and (not B)) or (not C) after gate_delay;
gate_AOI1.vhdl: Y <= not ( (A and B) or C ) after gate_delay;
gate_AOI1A.vhdl: Y <= not ( ((not A) and B) or C ) after gate_delay;
gate_AOI1B.vhdl: Y <= not ( (A and B) or (not C) ) after gate_delay;
gate_AOI1C.vhdl: Y <= not ( ((not A) and (not B)) or C ) after gate_delay;
gate_AOI1D.vhdl: Y <= not ( ((not A) and (not B)) or (not C) ) after gate_delay;
gate_AOI5.vhdl: Y <= not ( ((not A) and B and C) or (A and (not B) and (not C)) ) after gate_delay;
gate_AX1.vhdl: Y <= ((not A) and B) xor C after gate_delay; -- /!\
gate_AX1A.vhdl: Y <= not (((not A) and B) xor C) after gate_delay; -- beware of definition and inversion !
gate_AX1B.vhdl: Y <= ((not A) and (not B)) xor C after gate_delay; -- beware of definition !
gate_AX1C.vhdl: Y <= (A and B) xor C after gate_delay; -- /!\ mistaken with AX1 in the guide ?
gate_AX1D.vhdl: Y <= not(((not A) and (not B)) xor C) after gate_delay;
gate_AX1E.vhdl: Y <= not((A and B) xor C) after gate_delay;
gate_AXO1.vhdl: Y <= (A and B) or (B xor C) after gate_delay;
gate_AXO2.vhdl: Y <= ((not A) and B) or (B xor C) after gate_delay;
gate_AXO3.vhdl: Y <= (A and (not B)) or (B xor C) after gate_delay;
gate_AXO5.vhdl: Y <= ((not A) and B) or ((not B) xor C) after gate_delay;
gate_AXO6.vhdl: Y <= (A and (not B)) or ((not B) xor C) after gate_delay;
gate_AXO7.vhdl: Y <= ((not A) and (not B)) or (B xor C) after gate_delay;
gate_AXOI1.vhdl: Y <= not ((A and B) or (B xor C)) after gate_delay;
gate_AXOI2.vhdl: Y <= not (((not A) and B) or (B xor C)) after gate_delay;
gate_AXOI3.vhdl: Y <= not ((A and (not B)) or (B xor C)) after gate_delay;
gate_AXOI4.vhdl: Y <= not ((A and B) or ((not B) xor C)) after gate_delay;
gate_AXOI5.vhdl: Y <= not (((not A) and B) or ((not B) xor C)) after gate_delay;
gate_AXOI7.vhdl: Y <= not (((not A) and (not B)) or (B xor C)) after gate_delay;
gate_CLKINT.vhdl: Y <= A after gate_delay; (just a buffer)
gate_DFN1.vhdl: Q<=D after gate_delay; (always enabled)
gate_DFN1C0.vhdl: Q<=D after gate_delay;
gate_DFN1C1.vhdl: Q<=D after gate_delay;
gate_DFN1E0.vhdl: Q<=D after gate_delay;
gate_DFN1E0C0.vhdl: Q<=D after gate_delay;
gate_DFN1E0C1.vhdl: Q<=D after gate_delay;
gate_DFN1E0P0.vhdl: Q<=D after gate_delay;
gate_DFN1E0P1.vhdl: Q<=D after gate_delay;
gate_DFN1E1.vhdl: Q<=D after gate_delay; (enable when E=1, no clear)
gate_DFN1E1C0.vhdl: Q<=D after gate_delay; (enable when E=1, clear when C=0)
gate_DFN1E1C1.vhdl: Q<=D after gate_delay; (enable when E=1, clear when C=1) => bug !
gate_DFN1E1P0.vhdl: Q<=D after gate_delay;
gate_DFN1E1P1.vhdl: Q<=D after gate_delay;
gate_DFN1P0.vhdl: Q<=D after gate_delay;
gate_DFN1P1.vhdl: Q<=D after gate_delay;
gate_INV.vhdl: Y <= not(A) after gate_delay;
gate_MAJ3.vhdl: Y <= (A and B) or (A and C) or (B and C) after gate_delay;
gate_MX2.vhdl: Y <= A after gate_delay when S='0'
else B after gate_delay;
gate_MX2A.vhdl: Y <= (not A) after gate_delay when S='0'
else B after gate_delay;
gate_MX2B.vhdl: Y <= A after gate_delay when S='0'
else (not B) after gate_delay;
gate_MX2C.vhdl: Y <= (not A) after gate_delay when S='0'
else (not B) after gate_delay;
gate_NAND2.vhdl: Y <= not (A and B) after gate_delay;
gate_NAND3A.vhdl: Y <= not (((not A) and B) and C) after gate_delay;
gate_NAND3B.vhdl: Y <= not (((not A) and (not B)) and C) after gate_delay;
gate_NAND3.vhdl: Y <= not ((A and B) and C) after gate_delay;
gate_NOR2A.vhdl: Y <= not((not A) or B) after gate_delay;
gate_NOR2.vhdl: Y <= A nor B after gate_delay;
gate_NOR2B.vhdl: Y <= not((not A) or (not B)) after gate_delay;
gate_NOR3.vhdl: Y <= not ((A or B) or C) after gate_delay;
gate_NOR3A.vhdl: Y <= not ((not A) or B or C) after gate_delay;
gate_NOR3B.vhdl: Y <= not ((not A) or (not B) or C) after gate_delay;
gate_NOR3C.vhdl: Y <= not ((not A) or (not B) or (not C)) after gate_delay;
gate_OA1A.vhdl: Y <= ((not A) or B) and C after gate_delay;
gate_OA1B.vhdl: Y <= (A or B) and (not C) after gate_delay;
gate_OA1C.vhdl: Y <= ((not A) or B) and (not C) after gate_delay;
gate_OAI1.vhdl: Y <= not ((A or B) and C) after gate_delay;
gate_OR2.vhdl: Y <= A or B after gate_delay;
gate_OR2A.vhdl: Y <= (not A) or B after gate_delay;
gate_OR2B.vhdl: Y <= (not A) or (not B) after gate_delay;
gate_OR3.vhdl: Y <= (A or B) or C after gate_delay;
gate_OR3A.vhdl: Y <= ((not A) or B) or C after gate_delay;
gate_OR3B.vhdl: Y <= ((not A) or (not B)) or C after gate_delay;
gate_OR3C.vhdl: Y <= ((not A) or (not B) or (not C)) after gate_delay;
gate_XA1.vhdl: Y <= (A xor B) and C after gate_delay;
gate_XA1A.vhdl: Y <= (not (A xor B)) and C after gate_delay;
gate_XA1B.vhdl: Y <= (A xor B) and (not C) after gate_delay;
gate_XA1C.vhdl: Y <= (not (A xor B)) and (not C) after gate_delay;
gate_XNOR2.vhdl: Y <= not (A xor B) after gate_delay;
gate_XNOR3.vhdl: Y <= not ((A xor B) xor C) after gate_delay;
gate_XO1.vhdl: Y <= (A xor B) or C after gate_delay;
gate_XO1A.vhdl: Y <= (not (A xor B)) or C after gate_delay;
gate_XOR2.vhdl: Y <= A xor B after gate_delay;
gate_XOR3.vhdl: Y <= (A xor B) xor C after gate_delay;
gate_ZOR3.vhdl: Y <= (A and B and C) or ((not A) and (not B) and (not C)) after gate_delay;
gate_ZOR3I.vhdl: Y <= not ((A and B and C) or ((not A) and (not B) and (not C))) after gate_delay;
You will recognize the basic logic gates : AND, OR, XOR, MUX and their variants with inverted inputs or outputs (XNOR, NOR, NAND).
The letter at the end describes how many inputs are inverted (useful for bubble-pushing). A=1 inverted input, B=2, C=3... (though the rule seems broken in the AXx gates, double-check the definitions !)
Composite gates use single letters : A=AND, O=OR, X=XOR, I=Inverter
As far as I can remember, this nomenclature dates back to the Actel ACT1 family (late 80s), I remember looking at thick printed manuals to get the right gate for a design that I wanted to fit in the A1020 chip, back in 1997 in school :-) This has been ported from the antifuse to the flash devices and it's another reason why I'm familiar with the A3P family.
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