The system starts to work !

With the most fundamental problems "mostly solved", I can see my new code working in a promising manner.

Here is the new README.txt :

file README.txt
created sam. août 10 16:03:22 CEST 2019

WHAT :

The new version of the PA3 gates library is more compact
and provides much more insight into the logic's dynamic behaviour.
Configuration relies a lot on the runtime generics option of the
recent GHDL simulator, with the -g command line parameter.

WHY :

This tool enhances the classic ProASIC3 gates library
for design verification and "Design For Test".
It helps build test vectors and prove they can catch all the possible faults.
It also helps ensure that a complex boolean function has
no "blind spot" with unused intermediary combinations.

A non-boolean value can be injected and propagated through
the logic gates, to highlight the "logic cone" of the circuit,
which can greatly help during debug/development.

HOW :

The provided script runme.sh generates the big files with all
the definitions, then runs a couple of tests (three XOR2 chained)
as a self-test as well as demonstration of the use of the
new extra features of this library.

* VHDL source code only needs to include :

Library proasic3;
    use proasic3.all;

(just like before)

* The top level simulation file must include these 2 generics :

  generic (
    gate_select_number: integer := 0;
    bit_select_number: integer := -1
  );

The default values do nothing, but when they are changed,
the selected gate is affected/altered.
These values can be changed post-elaboration by GHDL's command line.

* A clock signal is required for sampling the gates' states
(avoiding false results due to transients)

  signal clock : std_logic := '0';

* The clock and the generics are fed into an entity
that does some of the dirty work behind the scene:

  rg: entity register_generics port map(
       gate_select_number => gate_select_number,
       bit_select_number => bit_select_number,
       clock => clock);

When "clock" changes to value '1' then the values of all the detected gates
are sampled and the histogram is updated.
The histogram is shown when  "clock" changes to value 'X'.


TODO :
  - "fast" option without instrumentation
  - sequential gates
  - tiny gates (1 and 0 input)
  - restrict the gates that will be sampled or altered.
  - sed scripts to filter the outputs
NOFIX :
  - coarse timing (everybody has 1ns latency)
  - 2^31 simulation cycles maximum

The archive is going live soon...