The Kobold is advertised to handle 16 bit instructions, but everything is 8 bit. Even the microcode is only 8 bit wide. How does it work ?

[ What you need to know for the examples: The program counter is in register R7 (as on the PDP11), and is copied into address register PC when needed. The lowest bit of the PC is always 0.]

EXAMPLE: 16-bit ADD

As example, take an instruction that adds (X+6) to register R4:

 add (X+6),R4 

The instruction is split into two parts, that operate almost independent of each other:

The first byte of the instruction is fetched from (PC) into the micro-program counter. From here, the micro-instructions determine the operation:

• First part:
• load the LSB of the 16bit accumulator with (X+6), (the LSB part)
• load the MSB of the 16bit accumulator with (X+6),  (the MSB part)
• fetch an instruction byte from (PC+1) into the micro-program counter (changing flow of the microcode). 

This instruction byte tells to add R4 (16 bits) to the accumulator and store the result back to R4:

• Second part:
• add the LSB of (WP+4) to the LSB of the accumulator
• add the MSB of (WP+4) to the MSB of the accumulator
• store the LSB of the accumulator back into (WP+4) (the LSB part of R4)
• store the MSB of the accumulator back into (WP+4) (the MSB part of R4)

The next section of the microcode will increment the PC and start the next instruction:

• connect the LSB of the PC (from the address registers) to the B-input of the adder of the ALU. The value 2 will be provided to the A-input of the ALU, so the byte value P+2 will be put in the accumulator.
• fetch the MSB of the pc from R7 [in the workspace] and put it into the accumulator, to make 16 bits complete.
• move the 16-bit accumulator contents to the pc in the address register set.
• fetch the next instruction from (PC) into the micro-program counter.
       ( from here, the micro-instructions for the next instruction are executed )

EXAMPLE: 8 bit immediate load

There are also instructions that have a single opcode byte, followed by an 8-bit immediate operand or z-page location. Branch instructions are  an example of this.

As example, load register R3 with value 0x80:

mov #0x80,R3

• load the LSB of the accumulator from (PC+1)
• load the MSB of the accumulator with zero
• store the LSB of the accumulator in (WP+3)  (the LSB part of R3)
• store the MSB of the accumulator in (WP+3)  (the MSB part of R3)

Finally, the pc is incremented and the next instruction is fetched, as in the previous example.