It seems that with a little thought I should be able to flip the impl into a single cycle design. The sticking point is that direct addressing the ROM means two cycles; one to load the instruction from the ROM and a second cycle to use the instruction to direct address the ROM and execute. 

It's pretty clear that it cannot be done.

So if I wanted to move to single cycle then I need to entirely separate program memory from data memory. The current design allows direct addressing either the RAM or the ROM so the ROM is multipurposed and this is where the issue lies. 

If alternatively I entirely separate the program memory and data then the ROM is used only to provide instructions and the direct addressing applies only to RAM. 

If I have lookup tables in ROM that I need for calcs or whatever then they would need to be copied to RAM, which I can do using immediate addressing to supply the data. 

Restrictng direct addressing to RAM only means I can ditch the instruction registers. 

Single cycle avoids the complexity arount the multi cycle, 3 phased approach I currently have.

Have to try the Verilog simulation and see what gives.