What you have all been waiting for....

The first version of the schematic for the CPU was just uploaded to the file section !

A few things were added:

• Provision for reading and writing bytes from/to memory. Address bit A0 will select low or high byte (as with most processors). Writing bytes will need software assistance. Single-cycle reading and writing of 16-bit words is of course still possible.

• The 64-word Zero page has got companion of another 64-word zero page. The second zero page is called the vector page, and is automatically selected whenever zero-page contents is written to the PC or D0 register. This is ment to be used for frequently accessed subroutines. A call can get its address from the zero page, saving space for an immediate value in the program code. The D0 register can also be used to store a value in the vector page.

The connectors of the CPU will probably change.

Explanation of schematic will be done in a next log.

Number of chips grew slightly above 40, it is now 43. 

[ edit: schematic updated today, 20191023 ]