I tried out the Multi-boot Multicomp build over the last couple of days on my Multicomp FPGA build and it is really sweet (compliments to the author/compiler - Rienk H. Koolstra). It would be a nice port to this card since it's a superset of all of the builds that I have done so far. From the features list of the page - the system's main specifications are:

• New ROM monitor with multi-boot capability, Format, Getsys and Putsys tools and debug capabilities. No BASIC in ROM.
• SD-HC capable card controller. Init at 250 kHz, running at 25 MHz.
• Improved keyboard definition featuring external keymap and added key functionality.
• Multi volume disk system, which currently supports upto 253 8MB disk volumes (which uses 2GB+ on the SD-card). All these volumes can be loaded with a separate OS bootimage.
• OSes configured with 3 drives: A:, B: and C:. A: for the system drive (holding the volume booted from) while B: and C: can be assigned and re-assigned one of the remaining volumes. Also a RAM disk is available for CP/M 2 and CP/M 3 systems.
• Y2k compatible system clock (date and time) for all OSes.
• Included are CP/M 2.2, Dos+ 2.5, CP/M 3.0, MPMII 2.1, ZSDOS 1.1/ZCPR2, ZPM3/ZCCP and NASCOM ROM Basic

There are two possible hurdles to overcome. The first is the MMU and the second potential hurdle is the SD card interface.

MMU Design

There are differences between the MMU in this implementation and the one currently in the PSoC. The current bank switch is for a single bank with selectable size. The MMU design has 4 banks which select one of 64 16KB banks. The base address for each of the bank is written by first writing to an offset register and then writing to the particular map register. The VHDL code for the MMU is here.

This can be implemented as a pair Z80 I/O addresses with one for the register select and another for the table value at that offset. The table consists of four registers which are 6 bits each (or 5 bits for 512KB).

The hardware seems fairly straightforward. The MMU logic is labeled as MMU4 and looks like:

This adds another level of multiplexer to the SRAM address lines.
The current page that drives the MMU1 gets changed to go through the new level of multiplexer. My assumption is that PSOC Creator will reduce the logic automatically.
The HEX file from Multiboot Multicomp gets converted into a C array with srec_cat as previously done and added to the project. The Z80 IO handler gets updated to add handlers for the new Memory Mapper. The Harware_Config.h file gets updated to add the new Memory Map (USING_MEM_MAP_4) and top level design (MULTIBOOT_CPM). This is very similar to the 9-Chip CP/M design described in a previous blog.

Can't test it with real hardware at the moment but it did compile and I checked it into the Project GitHub.
That did eat up some PSoC resources (mostly in the additional control registers), but there's still room.