I've cleared my agenda (it wasn't too busy anyway) this weekend to assemble both B1 and B2, which correspond to both TIMERS and CREG. I'm still missing some ICs (mainly, some 4-bit binary counters) that should arrive soon, so I won't be able to carry out too many tests.

Meanwhile, analisys and design of the remaining units (TOD, SDR and ICR) is around 75% complete. I'm hoping to start working on their schematics by the end of October.