During the design I chose current limiting resistors that were low enough to properly drive the chip being tester, but not so low as to damage the chip if the IO is being driven by opposing levels, eg driving 5v from the tester into a pin that is currently an output with a low value. In this situation the current limiting resistor prevents damage to get test device and the circuit under test.

However I came across this recently in the Phillips HCT User Guide, in section 8.2 "Push-pull outputs", it says ...

"A shorted output will also cause the maximum DC current rating to be exceeded. However, one output may be shorted for up to 5 s without causing any direct damage to the IC."

There is more info on that page.

Assuming most folk will be working with CMOS then I expect this to be true of most/all? devices and so my current limiting resistors could have been smaller still or perhaps non-existent as long as the tester only enabled it's pins momentarily to test the device and then went back to hi Z.

This is intuitive I think as any damage would be caused by heating and so a very short pulse would cause very little heat.

Thus is just an observation for a possible simplification of this setup.

The high value resistors on the other test pin of each pair is still needed to facilitate the tristate tests. If you don't care about those tests then the tester world work without any resistors and using only half the GPIO pins. But I really liked the idea that this device would be able to make strong assertions about all output types. I believe this tester would also correctly test/identify open collector variants.

https://assets.nexperia.com/documents/user-manual/HCT_USER_GUIDE.pdf