Did a build for the RETRO-EP4CE15 card. The build uses the 1MB of external SRAM as 64 banks of 16KB each. The banks are in the CPU address range of 0xC000-0xDFFF. There is a bank control register which initializes to bank=0 at power up or reset.

The 6800 CPU has a total of 60KB SRAM 9addressable. The rest of the RAM is internal to the EP4CE15 FPGA. The CPU memory map is:

--    Memory Map
--        x0000-x7fff - 32KB Internal SRAM
--        x8000-xbfff - 16Kb SRAM bank (64 banks)
--        xc000-xefff - 12KB Internal SRAM
--        xf000-xffff - 4 KB ROM (minus I/O space)
--        xfc00-xfcff - I/O space
--            xfc18-xfc19 - VDU/UART (6850 Interface)
--            xfc28-xfc29 - UART.VDU (6850 Interface)
--            xfc30 - Bank Select register (r/w)

The 12KB of SRAM could be initialized at boot and could function as a ROM space for an O/S, etc.

Build is loaded in GitHub.