I'm happy to report some progress made on the VDC-II project. I finished the CPU-to-video RAM interface. This includes block write and block copy functions from the original Commodore 8563 VDC chip. Only one small problem...

If you try to use the VDC-II chip as documented by Commodore, where you poke a register address, then wait for the chip to be ready, then poke a data value into a register, the DMA engine (what I call the Memory Port Engine, or MPE) corrupts video memory during a block operation.

However, if you poke the address, then poke the data, then wait on the ready flag, everything works perfectly! This breaks backward compatibility with Commodore's VDC, which makes me sad. It should work both ways; but, at least I have a viable software work-around.

Next steps are to implement the video fetch logic and the memory bus arbiter that will keep the different modules from stepping on each other's toes. If I can fix the aforementioned bug, that'd be great; but it's not a priority for me.