By whygee on Wednesday 22 February 2012, 04:00

Today is a big milestone : a tiny implementation of the YASEP has executed tens of instructions !

  phase='1' PC=3FE  RAM=0000  Result=0000 DST=0  R1=???? R2=???? R3=???? R4=????
  phase='1' PC=3FE  RAM=0000  Result=0000 DST=0  R1=???? R2=???? R3=???? R4=????
  *** releasing reset *** 
  phase='1' PC=3FE  RAM=0000  Result=0000 DST=0  R1=???? R2=???? R3=???? R4=????
  phase='1' PC=3FE  RAM=1009  Result=0000 DST=0  R1=???? R2=???? R3=???? R4=????
  phase='0' PC=000  RAM=1009  Result=0000 DST=0  R1=???? R2=???? R3=???? R4=????
  phase='1' PC=002  RAM=1234  Result=1234 DST=1  R1=???? R2=???? R3=???? R4=????
 writing 1234 to R1
  phase='0' PC=004  RAM=4009  Result=4009 DST=1  R1=1234 R2=???? R3=???? R4=????
  phase='1' PC=006  RAM=5678  Result=5678 DST=4  R1=1234 R2=???? R3=???? R4=????
 writing 5678 to R4
  phase='0' PC=008  RAM=1115  Result=1115 DST=4  R1=1234 R2=???? R3=???? R4=5678
  phase='1' PC=00A  RAM=4321  Result=5555 DST=1  R1=1234 R2=???? R3=???? R4=5678
 writing 5555 to R1
  phase='0' PC=00C  RAM=1117  Result=234B DST=1  R1=5555 R2=???? R3=???? R4=5678
  phase='1' PC=00E  RAM=0100  Result=AAAA DST=1  R1=5555 R2=???? R3=???? R4=5678
 writing AAAA to R1
  phase='0' PC=010  RAM=220A  Result=5556 DST=2  R1=AAAA R2=???? R3=???? R4=5678
  phase='1' PC=010  RAM=330A  Result=0002 DST=2  R1=AAAA R2=???? R3=???? R4=5678
 writing 0002 to R2
  phase='0' PC=012  RAM=330A  Result=0002 DST=2  R1=AAAA R2=0002 R3=???? R4=5678
  phase='1' PC=012  RAM=2408  Result=0003 DST=3  R1=AAAA R2=0002 R3=???? R4=5678
 writing 0003 to R3
  phase='0' PC=014  RAM=2408  Result=0003 DST=3  R1=AAAA R2=0002 R3=0003 R4=5678
  phase='1' PC=014  RAM=3408  Result=0002 DST=4  R1=AAAA R2=0002 R3=0003 R4=5678
 writing 0002 to R4
  phase='0' PC=016  RAM=3408  Result=0002 DST=4  R1=AAAA R2=0002 R3=0003 R4=0002
  phase='1' PC=016  RAM=1317  Result=0003 DST=4  R1=AAAA R2=0002 R3=0003 R4=0002
 writing 0003 to R4
....

You can find the source code there and play with the parameters :-)

The "microYASEP" is a compatible subset of the usual YASEP but with many limitations, like only 23 instructions (not yet all implemented), 2 cycles per instruction (no pipeline), not even data memory access... It is designed for tiny FPGAs and the core source code takes about 350 lines in VHDL. Data widths are 16 bits but could potentially be even smaller if needed (I'll have to check). I think it will run around 12 MIPS for the first system that will use it, it could be faster but this is useless.

This would not be possible without all the software tools I have written in the last months and years ! I can now assemble and export in hexadecimal or VHDL, create new custom configuration files with a few clicks, or tweak details at will. I have created a new system of "CPU profiles" that goes beyond the basic YASEP16/YASEP32 distinction.

The microYASEP is just one of the several possible microarchitectures possible with the YASEP. Later configurations will be faster, larger and with more features like the multiplier, shifter and memory interfaces... But with one first application and a running, basic core, the whole YASEP design can tune its details with more real-life feedback !

20200409:

I certainly felt proud and it was only the beginning :-)