It's time to update this, finally.

'myhdl2' was not a good name, the experiments 'myhdl.v2we' (van twee walletjes eten, a dutch pun) finally ended up in a merge which is now all under the name 'cyrite HDL'. And finally, it was time to say goodbye to the myhdl architecture.

The resulting ecosystem is now considered stable and is expected to have a longer life time.

Although I do generally not endorse to up-port working and verified code, it is now considered safe to migrate MyHDL legacy to the new cyHDL API. However, due to the modular nature and the strict interfaces, you may have to revisit and clean up your code.

The cyrite library comes with a few verification auxiliaries that make it easy to co-verify old MyHDL-generated HDL against a fresh cyHDL based port.

Some of the co-simulation methods from the jupyosys side will however no longer work, for example, Co-Simulation through VPI with GHDL or iverilog. The public cyrite version is as of now released only with a CXXRTL based co-simulation module only.

Also, all FPGA target specific setups are omitted. This is simply to cook down the memory usage and to avoid maintenance issues with specific boards.

After all, the link:

https://github.com/hackfin/cyrite.howto

Hit the Binder button and wait until the JupterLab starts up. Voila.