16-instruction, 12-bit Asynchronous CPU
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In the beginning, there were prerequisites...
Guess what these form..
One. XOR Gate. (well twelve but its still yewsless)
How will this help us in our addition journey? Well, the outputs of all gates except OR will also be interfaced with buffers to feed back into registers A and B (XOR into A, AND/NAND into B, depending on opcode,) which when combined with shifting will allow for addition in a maximum of 13 steps (recursive XOR & left-shift AND when fed back into A,B becomes the sum in 2^bit width + 1 for some reason,) but can be reduced with conditional jumps (i.e. break loop if B=0; addition completed.)
Once I build the registers, of course
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