uk4dshouseThis is a simple programable 4 button combination code interface module and as such can be used on a number of projects where a keyless lock control may be required. Only the PCB to generate the required signal to initiate a locking mechanism is shown, the locking mechanism is left to the user.
The PCB uses a combination of surface mount and through hole components which are all readily available, a steady hand and fine tip soldering iron will be required to mount the SMT components. For ease of construction the DIP's are mounted in sockets. Screw terminals are used to connect the 9V battery (5V min to 15V max), and output.
The condition as to whether set or unset is indicated by an LED, this can be extended above or remotely from the main board as per requirements.
The LED stays on when set.
Setting and un-setting is accomplished by entering a 4-button combination, the correct code turns on the LED indicating the system is set and the correct code turns off the LED.
An incorrect code sequence applies a reset to the system requiring the code sequence to be re-entered from the beginning.
The required code is set by jumpers (allowing the code to be changed easily), or links (hard coded, less flexible).
Hard coding negates the terminal posts simplifying construction, but makes changing the code less convenient
The links are arranged in groups of two links in a 4 x 4 matrix.
The column aligns with the corresponding switch, one column per switch.
The row aligns with the switch order from 1 to 4.
Taking S1 as an example.
Under S1 there are 4 links in the corresponding column, if the 1st link is made it assigns this as the 1st button in the code sequence,
If the 2nd link is made it assigns S1 as the 2nd button in the sequence etc.
The same methodology is applicable to all the buttons.
Therefore, in the accompanying picture the code is S2, S1, S3, S4
The PCB was designed using Eagle Cad and was manufactured at OSH Park.
Circuit Description
The circuit is realised using CMOS logic gates, a timer chip and a handful of discrete components.
The central element is the JK flip flop of which four are used, this requires the CD4027 IC which contains two flip flops, therefore two IC's are required.
The CD4027 is available with 16 pins in DIP and SMD, the pin out and functionality are the same irrespective of the package.
CD4027 truth table below:
| J | K | S | R | Q | CLK | Q | /Q |
| 1 | X | 0 | 0 | 0 | LH | 1 | 0 |
| X | 0 | 0 | 0 | 1 | LH | 1 | 0 |
| 0 | X | 0 | 0 | 0 | LH | 0 | 1 |
| X | 1 | 0 | 0 | 1 | LH | 0 | 1 |
| X | X | 0 | 0 | X | HL | NC | NC |
| X | X | 1 | 0 | X | X | 1 | 0 |
| X | X | 0 | 1 | X | X | 0 | 1 |
| X | X | 1 | 1 | X | X | 1 | 1 |
LH = Low to High transition, HL = High to Low transition, NC = No change, X = Don’t care.
For this application S and R inputs are both low therefore in this case the last three lines of the truth table can be ignored.
Therefore, the output state of the Flip Flop (FF), will be determined by the high level on the J or K input when the clock (CLK), is on the rising edge (LH).
Each of the first three keys of the keyboard are connect to the J input of a FF which detects the key state, with the key un-pressed the input is low (default is pulled low by a resistor), when the key is pressed the J input goes high when CLK changes LH. The causes the Q output to go high.
The 2nd FF is gated by a combination of the state of the previous 1st FF and CLK via an AND gate.
The CD4081 quad 2 input AND is available with 14 pins in DIP and SMD, the pin out and functionality are the same irrespective of the package
If the 1st FF’s output was high the 2nd FF’s output will go high when clocked, if the 2nd key was pressed.
The 3rd FF is gated by a 2nd AND gate (via the 2nd FF’s output), and CLK.
The K inputs of all the FF’s are connected together via the 4th key, pressing this provides a high level which on the next LH of the input CLK forces the Q outputs low and resets all the FF’s. If the key is un-pressed the input is held low (default is pulled low by a resistor).
In addition to the manual reset provided by the 4th key, a power on reset (POR), is provided by the capacitor/resistor (CR), network formed by the capacitor across switch 4 and the pull-down resistor on the K inputs.
When the power is applied the CR network provides a HL pulse to the K inputs and with the J inputs all pulled low by a resistor (J=L, K=H), the Q outputs are all low.
The output of the 3rd FF is connected to one input of a 2 input EXOR, the other input is connected to a POR network.
Single gate EXOR’s are available but their maximum operation voltage is 5.5V, which is at the low end of the CMOS operating voltage. In any event the intention is to operate the circuit at 9V
To this end, an EXOR using resistors, NFET’s and the 3rd AND gate was created.
The output of the EXOR gates CLK via the 4th AND gate to the input of the 4th FF were J=H and K=LH toggles the output of the FF. When Q=L the lock is set, when Q=H the lock is unset.
The status is indicated by the LED on the /Q output on the 4th FF, LED on set; LED off unset.
The clock is generated using a 555 timer configured in Astable mode with equal mark/space ratio this synchronises all the JK FF's.