32 Gigabit are available now, which would allow simultaneous parallel flags and greatly simplify how flags work at pain of higher price and wasteful utilization of the extra table space. Savings of my time and sanity may be worth the sacrifice certain ideals.

Also given some thought how busses fit together to make a CPU. I wish a pair of 32Kx8 SRAMs to ambidextrously feed registered arguments to this ALU's address bus. A latch at the exit will grab the result while tables are busy feeding valid address to other tables.

Latch can write the lookup back to either register bank, neither if only checking a flag, or mirror to both for later ambidextrous read.

8 way MUX will select a current flag output or preserved older state. Allowing choice of Zero, Carry, HalfCarry, Overflow, Sign, Odd, Old, and perhaps one other flag not yet decided. 

Selected flag and branching option (true, false, always, never) may then skip over the next instruction (for example a long jump) without wasting time to fetch and dismiss it. Decision is not triggered by the instruction being skipped.

Getting tired. I need to sleep on this plan and revise tomorrow.