Now that we have a working GCC toolchain, let's write a program to test the External SRAM. Need to use the patch that fixes the timeout for srecord loading. Using this patched version of the srecord file.
I'm using a GitHub repo to transfer data back and forth to my PC.
Also, upgraded to Quartus version 20.1. It is very slow.
Test of External SRAM passes:
* Test External SRAM * External SRAM on the RETRO-EP4CE15 card goes from 0x300000 to 0x3FFFFF (1 MB) * External SRAM only supports 8-bit accesses * TUTOR14 uses SRAM from 0x000000 to 0x000800 RAMSTART = 0x300000 RAMEND = 0x3FFFFF ACIASTAT = 0x010041 ACIADATA = 0x010043 * Code follows .ORG 0x001000 * CHECK FIRST LOCATION BY WRITING/READING 0x55/0xAA STARTTEST: MOVE.L #RAMSTART,%A0 MOVE.B #0x55,%D0 MOVE.B %D0,(%A0) NOP MOVE.B (%A0),%D1 CMP.B %D0,%D1 BNE FAIL MOVE.B #0xAA,%D0 MOVE.B %D0,(%A0) NOP MOVE.B (%A0),%D1 CMP.B %D0,%D1 BNE FAIL * WRITE INCREMENTING PATTERN MOVE.B #0X00,%D0 MOVE.L #RAMSTART,%A0 MOVE.L #RAMEND+1,%A1 CHKBLKS: MOVE.B %D0,(%A0)+ CMP.L %A0,%A1 BEQ DONEFILL ADDI.B #0x01,%D0 BRA CHKBLKS DONEFILL: * READ BACK INCREMENTING PATTERN MOVE.B #0X00,%D0 MOVE.L #RAMSTART,%A0 MOVE.L #RAMEND+1,%A1 LOOPCHK: MOVE.B (%A0)+,%D1 CMP.B %D0,%D1 BNE FAIL CMP.L %A0,%A1 BEQ DONECHK ADDI.B #0x01,%D0 BRA LOOPCHK DONECHK: * PRINT 'Pass' MOVE.B #0x0A,%D0 JSR OUTCHAR MOVE.B #0x0D,%D0 JSR OUTCHAR MOVE.B #'P',%D0 JSR OUTCHAR MOVE.B #'a',%D0 JSR OUTCHAR MOVE.B #'s',%D0 JSR OUTCHAR MOVE.B #'s',%D0 JSR OUTCHAR RTS FAIL: * PRINT 'Fail' MOVE.B #0x0A,%D0 JSR OUTCHAR MOVE.B #0x0D,%D0 JSR OUTCHAR MOVE.B #'F',%D0 JSR OUTCHAR MOVE.B #'a',%D0 JSR OUTCHAR MOVE.B #'i',%D0 JSR OUTCHAR MOVE.B #'l',%D0 JSR OUTCHAR RTS * OUTPUT A CHARACTER IN D0 TO THE ACIA OUTCHAR: BSR WAITRDY LEA ACIADATA,%A1 MOVE.B %D0,(%A1) RTS * WAIT FOR THE SERIAL PORT TO BE READY WAITRDY: LEA ACIASTAT,%A1 LOOPRDY: MOVE.B (%A1),%D1 ANDI.B #0x2,%D1 BEQ LOOPRDY RTS
Made significant improvements to above code and checked it into GitHub here.
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