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Addition works.

A project log for ICE-CPU MK II

Simple 16 bit soft-core CPU for FPGAs written in VHDL (previously verilog)

marioMario 07/29/2020 at 08:170 Comments

I think I finished writing the CPU up. Missing are the ROM and RAM.

But I only tested load and addition commands yet. TODO: Test every instruction

See:

What can be seen here?
load 5 into register 0
load 9 into register 1
load 2a into register 3 (Output address)
Add reg 0 and 1, save into reg 2

Display result (0x000e) at address (0x002a)

Looking good.

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