VHDL is a strongly typed language : you can define types that, though similar, can't intermix unless you cast them. This is good™ for code robustness. As long as you get them right. My recent code used strong typing to prevent mixing two similar-looking types, that I finally illustrated on this diagram:

The two types share the "signedness" trick where a number less than 1 indicates a port. The differences are significant though:

• One points to an input while the other points to an output.
• A positive sink number must also specify the gate's input number, encoded in the 2 LSB.

At one point I must have been confused and the corresponding diagram made no sense... sink_number_type was used instead of driver_number_type and sinks would point to sinks. That's a virtue of thorough documentation: it helps catch logic errors :-)

The above diagram and the one below are the keys to understand how the netlist is structured. Each sink points to their driver, and each driver points to one sink or a list of sinks. Easy to say, delicate to code :-)

So the confusion is now cleared and I can resume development.

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And the result is there : LibreGates_20201202.tbz