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A project log for Libre Gates

A Libre VHDL framework for the static and dynamic analysis of mapped, gate-level circuits for FPGA and ASIC. Design For Test or nothing !

yann-guidon-ygdesYann Guidon / YGDES • 05/26/2023 at 19:04•1 Comment

... evolves !


I did a lot of work and dev using the 2015 tarball version (0.35-dev packaged by RedHat in 2017) and today Fedora 38 has v1.0-dev, while v3.0 has been released a few weeks ago. I'd like to get it on my computer but there is no .RPM yet.

This breaks some scripts and I'll have to hack and reverse-engineer more to get the scripts functional again. This would enable me to resume work on some borked/incomplete parts of the tools...

I haven't touched the codebase in 2 years now and it's getting a bit dusty :-/
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05/26/2023 at 11:06 • 10 comments
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SHAOS wrote 05/27/2023 at 04:13 • point

does it work? last time when I checked (like 10 years ago) it was not functioning properly :)

I'm so happy that I switched to Verilog and found Verilator in 2018 ;)

I'll come back to VHDL as soon as GHDL becomes as perfect as Verilator :)

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