The version 3 boards came back and there were a couple of errors that needed to be worked around, but in essence it works. I'm going to have a 3.0.1 board made that fixes the couple of mistakes (a couple of clearance issues and moving one of the outputs from the TPID pin to the TPIC pin, which is less sensitive to loading).

The v3 design uses two SSRs - one to hold the system power on for the duration of the sequence and another to switch the load on and off. The load is 3 9.1kΩ resistors in parallel, for a total of around 4.75 watts, plus another quarter watt or so for the LV side. The load is switched on and off at about a 50% duty cycle to try to fool the Intelliflow into thinking there's a busy washing machine there. But the goal of v3 has been reached - when the system is off the leakage of the power-hold SSR is practically zero.