This project is intended to be a software project but a description of the hardware is necessary as a reference to understand the resources available to the software.
Features
- Runs on Altera Cyclone IV and V FPGA Cards
- 68000 CPU
- 32 MB SDRAM
- Host Serial Connection (USB to Serial)
- Video Display Unit (VDU)
- VGA
- PS/2 keyboard
FPGA Cards
- Initially running on Cyclone V FPGA card (very small resource utilization)
- Ported to Cyclone IV EP4CE15 FPGA card - compiled
- Resource efficient but probably wouldn't fit into anything smaller than an EP4CE10.
Flow Status Successful - Sun Sep 06 12:05:04 2020 Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Revision Name SOC Top-level Entity Name C5BoardToplevel Family Cyclone IV E Device EP4CE15F23C8 Timing Models Final Total logic elements 7,984 / 15,408 ( 52 % ) Total registers 3629 Total pins 134 / 344 ( 39 % ) Total virtual pins 0 Total memory bits 107,520 / 516,096 ( 21 % ) Embedded Mult 9-bit els 2 / 112 ( 2 % ) Total PLLs 1 / 4 ( 25 % )
TG 68000 Core
- 100 MHz?
- Wait states
- 32-bits of addresses connected?
32MB SDRAM
- Winbond W9825G6KH-6 133 SDRAM
- 4M x 16 bits x 4 banks
Host Serial Interface
- FT-230XS USB to Serial
- 115200,N,8,1
- USB B connector
Video Display Unit
- VGA
- PS/2 keyboard and Mouse
Memory Map
- 0x00000000-0x0000FFFF = ROM
- 0x00100000 - Framebuffer
- 0x0FFFFA - Variables
- 0x7FFFFE - The initial stack pointer
- 0x800000 = VGA controller
- Screen base address register
- 0x810000 = Peripherals
- Four counters, t0 through t3
- 0x810010-0x810016 = Divisor register for all four counters
- 0x81000e = Control word at which contains interrupt enable bits and status bits for counters t1 through t3.
- T0 acts as a prescalar for the other three timers, so with the system clock set to 112.5MHz, setting T0’s divisor to 1125 gives the other three timers a 100KHz base clock.
- 0x820000 = Audio controller
Discussions
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