fpga risc-v soc

Simple implementation of risc-v soc on fpga

misha

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Description

This repository contains an extremely simple implementation of the RV32I ISA
*Entirely written in Verilog.
*Every opcode need one clock cycle to execute, except memory operations(store/load).
*Used 1 port block ram ip for memory inteface
*Not designed with multiple RISC-V harts .
*The privileged ISA is not implemented.
*FENCE, FENCE.I and CSR instructions are not implemented.