// Main module - the ports for the FPGA, register map handling
module spi_pwm_micro_test(
	input wire clk, // 50 MHz clock, pin 27
	input wire bar_ss, // SPI chip select, pin 93
	input wire mosi, // SPI master output, pin 92
	input wire sck, // SPI clock, pin 99
	output wire miso, // SPI sidekick output, pin 101
	output wire led1, // LED1 pin 132
	output wire led2, // LED2 pin 134
	output wire led3, // LED3 pin 135
	output wire led4, // LED4 pin 140
	output wire led5, // LED5 pin 141
	output wire pwm_wire0, // PIN 60
	output wire pwm_wire1, // PIN 59
	output wire pwm_wire2, // PIN 56
	output wire pwm_wire3, // PIN 55
	output wire pwm_wire4, // PIN 47
	output wire pwm_wire5, // PIN 46
	output wire pwm_wire6, // PIN 43
	output wire pwm_wire7); // PIN 41

//////	
// Register map
reg [31:0] max_count_0;
reg [31:0] compare_val_0;
reg [31:0] max_count_1;
reg [31:0] compare_val_1;
reg [31:0] max_count_2;
reg [31:0] compare_val_2;
reg [31:0] max_count_3;
reg [31:0] compare_val_3;
reg [31:0] max_count_4;
reg [31:0] compare_val_4;
reg [31:0] max_count_5;
reg [31:0] compare_val_5;
reg [31:0] max_count_6;
reg [31:0] compare_val_6;
reg [31:0] max_count_7;
reg [31:0] compare_val_7;

// Initial values for the register map
initial begin
	max_count_0 <= 32'h02FAF080;
	compare_val_0 <= 32'h017D7840;
	
	max_count_1 <= 32'h02FAF080;
	compare_val_1 <= 32'h017D7840;
	
	max_count_2 <= 32'h02FAF080;
	compare_val_2 <= 32'h017D7840;
	
	max_count_3 <= 32'h02FAF080;
	compare_val_3 <= 32'h017D7840;
	
	max_count_4 <= 32'h02FAF080;
	compare_val_4 <= 32'h017D7840;
	
	max_count_5 <= 32'h02FAF080;
	compare_val_5 <= 32'h017D7840;
	
	max_count_6 <= 32'h02FAF080;
	compare_val_6 <= 32'h017D7840;
	
	max_count_7 <= 32'h02FAF080;
	compare_val_7 <= 32'h017D7840;
		
end

//////
// Registers for the SPI interface
wire spi_ready_write_data;
wire spi_ready_read_data;
wire [7:0] spi_register_address;
wire [31:0] spi_write_data;
reg [31:0] spi_read_data;

initial begin
	spi_read_data <= 32'h00000000;
end

// SPI module
spi_interface spi0(clk, bar_ss, mosi, sck, miso, spi_ready_write_data, spi_ready_read_data, spi_register_address, spi_write_data, spi_read_data);

// Register map in/out
always @(negedge clk) begin
	// Writing registers
	if (spi_ready_write_data == 1'b1) begin
		case (spi_register_address)
			8'd1 : max_count_0 <= spi_write_data;
			8'd2 : compare_val_0 <= spi_write_data;
			8'd3 : max_count_1 <= spi_write_data;
			8'd4 : compare_val_1 <= spi_write_data;
			8'd5 : max_count_2 <= spi_write_data;
			8'd6 : compare_val_2 <= spi_write_data;
			8'd7 : max_count_3 <= spi_write_data;
			8'd8 : compare_val_3 <= spi_write_data;
			8'd9 : max_count_4 <= spi_write_data;
			8'd10 : compare_val_4 <= spi_write_data;
			8'd11 : max_count_5 <= spi_write_data;
			8'd12 : compare_val_5 <= spi_write_data;
			8'd13 : max_count_6 <= spi_write_data;
			8'd14 : compare_val_6 <= spi_write_data;
			8'd15 : max_count_7 <= spi_write_data;
			8'd16 : compare_val_7 <= spi_write_data;
		endcase		
		
	end else if (spi_ready_read_data == 1'b1) begin
		case (spi_register_address)
			8'd0 : spi_read_data <= 32'hB7AADA2F;
			8'd1 : spi_read_data <= max_count_0;
			8'd2 : spi_read_data <= compare_val_0;
			8'd3 : spi_read_data <= max_count_1;
			8'd4 : spi_read_data <= compare_val_1;
			8'd5 : spi_read_data <= max_count_2;
			8'd6 : spi_read_data <= compare_val_2;
			8'd7 : spi_read_data <= max_count_3;
			8'd8 : spi_read_data <= compare_val_3;
			8'd9 : spi_read_data <= max_count_4;
			8'd10 : spi_read_data <= compare_val_4;
			8'd11 : spi_read_data <= max_count_5;
			8'd12 : spi_read_data <= compare_val_5;
			8'd13 : spi_read_data <= max_count_6;
			8'd14 : spi_read_data <= compare_val_6;
			8'd15 : spi_read_data <= max_count_7;
			8'd16 : spi_read_data <= compare_val_7;
			default : spi_read_data <= 32'h00000000;
		endcase		
		
	end
end

//////
// PWM modules
pwm_module pwm0(clk, max_count_0, compare_val_0, pwm_wire0);
pwm_module pwm1(clk, max_count_1, compare_val_1, pwm_wire1);
pwm_module pwm2(clk, max_count_2, compare_val_2, pwm_wire2);
pwm_module pwm3(clk, max_count_3, compare_val_3, pwm_wire3);
pwm_module pwm4(clk, max_count_4, compare_val_4, pwm_wire4);
pwm_module pwm5(clk, max_count_5, compare_val_5, pwm_wire5);
pwm_module pwm6(clk, max_count_6, compare_val_6, pwm_wire6);
pwm_module pwm7(clk, max_count_7, compare_val_7, pwm_wire7);

assign led1 = ~bar_ss;
assign led2 = 1'b0;
assign led3 = 1'b0;
assign led4 = 1'b0;
assign led5 = 1'b0;


endmodule