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A project log for ATLAS CPU-8

An attempt at an 8-bit modified Harvard-architecture TTL computer for my senior project.

hayden-bHayden B. 11/10/2020 at 23:110 Comments

Hello, this is the first log entry for the ATLAS CPU-8. I've been working on it for the past three weeks, and what I have so far is a somewhat functional Logisim implementation. As of the time of posting, I have written and tested 22 working operations (0 - 21). Once I'm done with the arithmetic operations, I'll move onto the program memory read/write ones and finally the jumps.

I am still thinking about how I will approach serial addressing, although I'm probably going to make it memory-mapped. I've also had thoughts about revising the data bus design, although I feel that it would be more trouble than it's worth.

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