The 4-to-1 bit multiplexers select input bits based on signals B and A.

"B" is VCYC inverted.

"A", the Row/Column selector, is /RAS clocked by the 28 MHz master clock.
This is /RAS delayed by 1/28th of a microsecond, which is 35 ns.

/CAS is /RAS clocked by CY3, which is half the 28 MHz master clock.
This is /RAS delayed by 1/14th of a microsecond which is 71 ns.

DRAM cycle frequency is 28/8 = 3.5 MHz.