StevenFuzix
Unfortunately, the 128KB RAM is too little for the system to run Fuzix. In theory, I could change the board a bit and swap the 32KB RAM chips for 512KB RAM. But every time I looked at the wires at the back of the board, I'm too afraid I will permanently damage the board. So, I give up...
Then I thought, let's make a new board with 2x AS6C4008 RAM chips based on the old design. It was easy to make the schematic in Kicad, but I thought it was an automated process to design the PCB from the schematic. How mistaken I was! In the PCB editor, I got stuck with a rats nest, and couldn't design a decent PCB. So, I gave up again...
Then again, someone must have designed a tiny and simple(!) 68000 PCB board with just RAM, ROM, and a UART without fancy components. Searching the internet and I found this: 68K-nano by Matt Sarnoff. This is exactly the design I was looking for!
68K-nano
I ordered and built this board, and it works fine for me. Made two minor changes:
- AT28C64B for EEPROM; these are in stock with me and pin compatible with the AT28C256.
- Added an 11.0592 MHz crystal to the UART; now it is easy to change the CPU clock speed without altering the divider in the BIOS.
This board runs stable at 24MHz (!) (Matt rated this at 12 MHz). I am now porting my BIOS to this board. After that, I can proceed the Fuzix port on the new board...
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Hi MacGyver, no I didn't try it (yet) but the designer (Matt Sarnoff) claimed it should work. I have read a lot about CF and 68K and indeed, the timing of the 68K is awkward (for this type of equipment). The /RD of the CF-card shout be *after* the CS of the card, but in 68K both are synchronised with the /AS. (The /RD is used to latch-out the data from the CF to the data bus and every /RD pulse will sent a new byte. An glitch on the /RD will end up in a lost byte).
So there are two solutions:
1) Delay the /RD by some nanoseconds. It can be done by a delay line (just some logic in a line), delay by using a flip-flop and the clock or (perhaps) by a resistor/capacitor delay.
2) Get the CS earlier. And that is what is happening in 68K-nano: the CS of the CF is just the A20 address-line. So the moment A20 becomes high, the CS is active for the CF. And that's nanoseconds before the /AS becomes active. (In "normal"/clasic design you use a 74HCT138/139 for address-decoding and use /AS for the /Enable; thereby synchronizing the CS with the /AS) The /RD is synchronised with the /AS in the 68K-nano design by the 74HC139 chip and thereby later.
The simple address decoding comes with a downside; the /CS could asserted by flowing tri-state address lines. But in that case only the chip is activated (a little more current) but there is no transaction of data, so it is harmless.
It's amazing that all that is capable in that 68K-nano design: Less is more!
@Peabody1929 : I like your Z80 design; in the 80's I also played with them. Perhaps I will build one...
Are you sure? yes | no
On your 68K-Nano, have you tried using the CF-Card? I have tried a CF-Card with the 68K and it does not work reliably in my design. There seems to be a setup issue: address, select and R/W signals must occur before CS (card select). I have tried a CF card with a Z80 and it works fine because the Z80 I/O cycle has a built in setup before the IORQ signal goes active. How does the CF interface/card work on the 68K-Nano ?
Are you sure? yes | no