Everything you wanted to know about configuring the TI-86 link port...

In the form of an Assembly Include-file which can be used in Zac, on the calculator... If you're crazy, like me, and don't mind sacrificing 6KB for some at-hand documentation.

I'll attach the actual file in this project's Files-Section....

https://cdn.hackaday.io/files/1797727691365248/iPort7.86p

View this one if your browser isn't showing monospace:

https://cdn.hackaday.io/files/1797727691365248/iPort7.86p.txt

A:TI-86 Port 7 Info/Defines

;TI's Link-Port

;Note that TI-OS watches the
;link-port in _getkey(?)
;which is called in the
;200Hz interrupt(?).
;Best:
; 1 disable ints
; 2 dont connect custom
;   harware until AFTER 1
; 3 dont call OS-supplied
;   keyboard funtions
; 4 disconnect custom hardware
;   before 5
; 5 restore Port 7 to TI-OS's
;   idle state
;   (call PORT7_restore)
; 6 reenable interrupts

;Port 7  :
;Internal:
;CPU I/O :    6V
;Buffers :    |
;   vv   :    $ 10K Resistor
;ID-<|-+------+  
;OD-|>-' :    V Diode
;OED-'   :    +------->< wire
;        :    $ 470 Resistor
;OT-|>-+--~-|< NPN Transistor
;OET-' | :    |
;IT-<|-' :   GND 


; Redrawn
;6V--~--+-|>|---+----->< wire
;   10K |  pL,Z}|  470
;.....  |{H,L,Z '---~----.
;CPU :..|..........   b  | c
; ID-<|-+  IT-<|-+--~--|< NPN
; OD-|>-'  OT-|>-':      | e
; OED-'    OET-'  :     GND

;Through Diode:
; ID = Input Buffer
; OD = Output Buffer
; OED = Output Enable for
;       Buffer to Diode 
;Through Transistor:
; OT = Output to Transistor
; OET = Output Enable for
;       Buffer to Transistor
;       (almost always ON=1)
; IT = Input Buffer ("from
;      Transistor" base)

; OET OED OT OD  Wire  ID
; v---unknown effect-------
; 0   0   X  X   pu?   pu?   
; 0   1   X  0   Z?    0
; 0   1   X  1   H     1
; ^---unknown effect-------
; best avoid "floating" base

;.--used by TI-OS for linking
;V
;  OET OED OT OD  Wire  ID
;H 1   0   0  X   pH    pH
;  1   0   1  X   vL    vL
;  1   1   0  0   hZ    0
;  1   1   0  1   dH    1*
;L 1   1   1  0   pL    0
;* UNKNOWN if CPU output has
; the high drive-strength to 
; overcome 470ohms to GND

; --------V--V-------------
; 1   1   1  1   H?    1*
; --------^--^-------------
; prb best to avoid competing
; drivers, though CPU driving
; high through 470 to GND may
; be OK, plausibly useful

;pL == pulled-Low through 
;      transistor/resistor.
;      6V/ID/OD/10K-pull-up
;      effectively isolated
;      from wire via reverse
;      diode (see hZ note)
;              470
; ~=      GND --~-->< wire
;     BUT: ID=0!!!
;
; pL is TI-OS's Link Low.
;  Effectively output-only.
;  Despite resistor, pulling
;  the wire high externally
;  will not be measured.
;  For that, see vL.

;pH == pulled-High 
;      through diode:
;  6V --~---+-|>|-->< wire
;  ID --<|--'
;             10K
; ~=      6V --~-->< ID=wire
;
; pH is TI-OS's Link Idle.
;  Bidirectional.
;  Wire/ID Reads High unless
;  other device pulls low
; This MIGHT also work with
;  similar bidir pulled-up
;  open-collector interfaces
;  such as i2c.
;  However beware 6V!
; Ironically, this MIGHT work
;  well with HIGHER-voltage 
;  OC/PU interfaces, since
;  diode should prevent e.g.
;  12V from reaching CPU.
;  Am presently working on
;  such and cant quite
;  convince myself to risk it

;dH == Driven High* from
;      CPU Output via Diode
;  OD=1 ---|>--+--|>|-->< wire
;  ID=1 ---<|--'
; depending on connected
; circuit, may override
; circuit's pulling wire low
; E.g. another TI-86 could
; activate its low-pulling
; transistor (see vL), yet 
; read the wire as high* 

;hZ == High-Impedance via
;      Reverse Output Diode:
;  OD=0 --|>--+--|>|-->< wire
;  ID=0 --<|--'
; note diode orientation
; effectively isolates
; wire and ID
;  OD=0 --|>--+--  -->< wire
;  ID=0 --<|--'
; May be useful e.g. with
; multiple devices on a bus 
; OR to 3V3 logic input w/
; external pull-up resistor

;vL == pulled-Low through
;      Voltage-Divider:
;      10K         470
;  6V --~---+-|>|-+--~-- GND
;  ID --<|--'     '-->< wire
;              470
; ~=     0.3V --~-->< ID=wire
;
; vL Can Be Useful
;   e.g. external 3V3 logic
;   outputs to TI-86
;         :logic output :
;         : __|__ __|__ :
;     3V3_:__7 \_._/ \,_:_GND
;         :..PNP.|.NPN..:
;                |
;      10K       |  470
;  6V --~--+-|>|-+--~---- GND
;  ID --<|-'
; NOTE: Logic MUST Drive 8mA
; (Also CPU In=High Threshold
;  Voltage unknown/untested)
; other I/O configs wont work
; pH: puts 6V INTO 3V3 output
;     Can be bad when Logic=H
; dH:  ditto worse, also ID=1
; pL: ID=0 regardless of wire
; hZ:  ditto

;port 7 (READ):
; TODO: VERIFY
;Bits 7-4 read-back config bit
; bit 7: =OET white wire
; bit 6: =OET red wire
; bit 5: =OED white
; bit 4: =OED red
;Bits 3,2 *usually* will, too
; bit 3: IT~=OT white
; bit 2: IT~=OT red
;Bits 1,0 read the "inputs"
;Though may differ per config
; bit 1: ID ~=white wire
; bit 0: ID ~=red wire

;port 7 (WRITE/Configure):
;.-bit 7: OET white wire
;|-bit 6: OET red wire
;|-bit 5: OED white
;|-bit 4: OED red
;|-bit 3: OT white
;|-bit 2: OT red
;|-bit 1: OD white
;|-bit 0: OD red
;|
;| "DIR"/OE  OUT(VAL)
;|  7 6 5 4  3 2 1 0 port bit
;|  4 3 2 1  4 3 2 1 port pin
;'> T T D D  T T D D
;   w r w r  w r w r  wht/red
;TI-OS/linking uses:
;C0 1 1 0 0  0 0 X X  pH  pH
;D4 1 1 0 1  0 1 X 0  pH  pL
;E8 1 1 1 0  1 0 0 X  pL  pH
;and rarely (on link error?):
;FC 1 1 1 1  1 1 0 0  pL  pL
PORT7_WpH_RpH =$C0
PORT7_WpH_RpL =$D4
PORT7_WpL_RpH =$E8
PORT7_WpL_RpL =$FC
;pL: input=0, wire pulled low
;pH: input=wire, pulled high
;vL: input=wire ~= pulled low
;dH: input=1, wire driven high
;hZ: input=0, wire high-Z 

PORT7_W_MASK =%10101010
PORT7_WpL    =%10101000
PORT7_WpH    =%10000000
PORT7_WvL    =%10001000
PORT7_WdH    =%10100010
PORT7_WhZ    =%10100000

PORT7_R_MASK =%01010101
PORT7_RpL    =%01010100
PORT7_RpH    =%01000000
PORT7_RvL    =%01000100
PORT7_RdH    =%01010001
PORT7_RhZ    =%01010000

;NOTE: PORT READ does NOT
; match last PORT WRITE
; (in lowest four bits)
;THUS: can NOT simply
; read/modify/write
;ALSO: can NOT simply read
; port 7 at program entry
; then restore that value
; before returning to TI-OS. 
;THUS CALL PORT7_restore, 
; or  USE  PORT7_TIOS_IDLE,
; AND THEN reenable interrupts
; before exit

PORT7_TIOS_IDLE =PORT7_WpH_RpH
;restore port 7 for TI-OS
; Dont forget to re-enable
; interrupts, thereafter
PORT7_restore:
 ld a,PORT7_TIOS_IDLE
 out (7),a
 ret


;E.G. Custom for 3V3-serial:
;                     wht red
;                     Rx  Tx
;C8 1 1 0 0  1 0 X X  vL  pH
;DC 1 1 0 1  1 1 X 0  vL  pL
PORT7_WvL_RpH =$C8
PORT7_WvL_RpL =$DC
;wh=input=vL prevents 6V from
;   feeding into 3V3 output.
;   Output must drive 8ma!
;red=output=pH ONLY SAFE HERE
;   because My converter has
;   a zener at Rx
; (OTW maybe use hZ
;  AND add pull-up to 3V3)
;Then in iUART3V3:
; TxLOW  =PORT7_WvL_RpL
; TxHIGH =PORT7_WvL_RpH