Magic-1 computer on Logisim

I inverted the latch outputs entering U47 in Faults & Interrupts.

This corrected a bug where the CPU was doing an NP fault right after reset.

With this, the fibonaci test seems to run fine (no way to check).

This will be the last modif for a while unless someone finds a bug.

All the code is on github on the link provided.

Time to go on other projects!

The original microcode was OK. There was some errors in the field decode. Polarity of CLKS and U43D was wrong.

Call just immediately return instead of executing the subroutine.

I had to tweak the microcode to make call work. The original microcode was adding 2 times the displacement, thus messing the return address. It's probably due to my implementation of the clock circuit with a state machine instead of a few delays.

So now, call and return work.

I'm currently testing the Fibonaci test. The code has been provided by Mr. Buzbee.

It's not yet confirmed to work, it seems to end prematurely with a halt.

Now, stepping works with NOPs. It's alive!

Added the original microcode from Buzbee's own files.

Added bus swappers on RAM and ROM memories to match the circuit.

Solved some bus conflicts.

With the ROM filled with NOPs; so far, it gets the first op from the ROM, but the bus address doesn't increment.

The microcode seems to be running, not sure what it's doing yet.

I modified Buzbee's code to generate the microcode from C instead of using scripts.

Some minor corrections to Logisim files.

logic74xxic

The logic74xxic needed some rework to upgrade to Logisim Ev. 3.4.1:

5-input gates corrected in all circuits

Flip-flops corrected, all chip corrected

Magic-1

The higher schematics were cleaned a lot, upgraded all the chips

Clock module is implemented with buffer instead of delays.