ATMEGA328P is the part that is found on inexpensive and generic Arduino-compatible boards.  ATMEGA328P is an older part but it is well supported in Arduino world.  It's what I've got.  If this was a commercial project, it would be better to use ATMEGA328PB or newer part in the ATmega family.  With '328P, there are 3 timers, 0, 1 and 2.  Each has unique features.  Timer1 is 16 bit and has most PWM features, so let's start with that one.  Timer0 is 8 bit and is used by Arduino code for delay() and millis().  Those functions are important, so don't use timer0.  Timer2 is also 8 bit and is also used by some functions.  Timer1 is used by servo libraries.  This project won't use servo PWM, so that should work.

Looking at the PWM timing diagram, there are 4 edges to generate.  2 rising and 2 falling edges.  This is a challenge because timer1 has 2 output compare modules.  Most of the PWM modes change state when the timer reaches an output compare match.  The PWM output then resets at the TOP count.  So how can we generate 2 PWM pulses with 180 degree phase shift?

• Software and interrupts:  This will work, but if the timing goes wrong, then the power stage might be damaged.  The interrupt service routine would have to be fast and reliable.
• External logic:  Make some arrangement of gates and flip-flop to generate the timing sequence.  The timer output can clock the logic and control the duty.  Basically take 1-phase PWM and switch it back and forth between the 2 phases.  This would work well, but it requires 2 external ICs.  Switching frequency will be half of the timer PWM frequency.
• Use 2 different timers, one for each PWM phase.  The timers need to be synchronized. Synchronizing 2 very different timers seems difficult.  This would be awful in ATTINY328P.  ATTINY328PB (and other ATMEGA parts) includes 2 extra 16-bit timers. These are copies of timer1 peripheral, so 2-phase or 3-phase PWM should be practical.  I'm not changing the chip for this project.
• Use one of the "phase correct" PWM modes to generate 2 symmetrical outputs.  In this mode, the timer counts up and down to generate a symmetrical triangle of timer megnitude.  The output compare OCR1A/B can trigger PWM edges on the upward and downward counts.  This can make PWM pulses centered on the clock TOP and BOTTOM states.  Unfortunately, phase correct PWM is a bit slow.

This project will focus on the phase correct method.  Maybe the other methods can be tried later.