When examining the piggy-back SRAM idea, I noticed the original design used this wiring:

R/!W --> inverted --> ROM !CS
ROMSEL --> inverted --> ROM !OE

This was a way to reduce EPROM access time. It would be activated early on, and then take only the shorter output buffer switch-on time to provide the data when selected.

Flash ROMs are not exactly like EPROMs, because they want the address to be stable while they are selected. If not, they internally start accessing a garbage address then try restarting when the address changes. With the original wiring, every read cycle will start an access. 

This probably explains why start-up tests that didn't involve the DRAM were not reliable. Most of the time, a test would run for seconds, but then crash.

At this point, I could either try using a 32-pin EPROM, or try swapping the !CS and !OE wires over.

This would ensure the address is always valid (!AS asserted), and as a bonus the !OE signal could be shared with piggy-backed SRAM chips.

I only have 28-pin EPROM chips so I'd have to modify tracks. And if I have to do that, I might as well save a step and modify tracks to suit the Flash ROM.

Here are the mods to be made on the underside:

Cut tracks at the red Xs, then make the purple wire.

This isolates the pin signal from !CE and routes it to !OE.

Now we need to isolate the signal that goes to !OE and route it to !CE.
Make the yellow wire to drive !CE.

Then turn over and cut the track marked with a red X.

Switch on, some tests running.

0 pulsing. Screen shows gradient of grey, because VIDLATCH increments background colours.
2 CRTC not initialised. LED pulses (VIA test)
4 CRTC not initialised. LED pulses (Iporttest)
6 CRTC not initialised. No pulsing so fail (memtest fail)

1 CRTC initialised. No pulsing so fail (SCC test)
3 CRTC initialised. No pulsing so fail (Crtcrwtest test)
5 CRTC initialised. No pulsing so fail (RAM test fail)
7 CRTC initialised. No pulsing so fail (screen RAM fail)

When the screen is initialised, it is just DRAM garbage, no characters.

Run mode (15) is a little better than before, because it does appear that the screen RAM is being written to, however this does seem random so I assume the software is running amok.

So I thought the ROM behaviour had improved but the RAM is still failing.

Then I checked the Exception report, it says the last instruction was in ROM.

ROM changed to Atmel 29F002T-70 chips, but these worsened the issues if anything at all.

UPDATE:

The original design swapped the signals over, but Jo's modern design does not. So all the mods I made above had to be undone! 

The swapping probably only needs doing if you are upgrading an original board to use Flash ROM. I have not got an old board so I cannot check this out.